Preparation method of source and drain regions and MOS device

Abstract

The invention discloses a preparation method for a source drain region and a metal oxide semiconductor (MOS) device manufactured according to the method. The method comprises the steps of providing a structure prior to preparation of the source drain region, and performing back carving on a substrate which is to form the source drain region so as to form a groove; forming a silicon oxide layer on the surface of the structure; depositing a silicon seed layer; depositing a mask layer, and utilizing the mask layer to fill the groove; enabling the mask layer located outside the groove and part of the mask layer in the groove to be removed; enabling the mask layer positioned in the groove to serve as a blocking part to remove the silicon seed layer and the silicon oxide layer, and exposing a light doping drain region positioned below a side wall; removing the remaining mask layer; performing epitaxial growth of silicon in the groove, filling the groove, burying the light doping drain region positioned below the side wall, and forming a pre-injection region; and performing ion injection on the pre-injection region to form the source drain region. According to the MOS device, electric leakage caused by short-channel effect generated along with shortening of grid length is restrained due to partial covering of the silicon oxide layer between the source drain regions, and power consumption of the MOS device is reduced.

Description

technical field [0001] The invention relates to semiconductor manufacturing technology, in particular to a method for preparing source and drain regions of a MOS (Metallic Oxide Semiconductor, metal oxide semiconductor) device and a MOS device manufactured according to the method. Background technique [0002] A conventional manufacturing process of an existing MOS device includes the following steps. [0003] A substrate 1, such as a silicon substrate, is provided on which shallow trench isolation (STI) 2 is formed, such as figure 1 shown. Ion implantation is performed on the substrate 1 to form an N-well and / or a P-well, and threshold voltage adjustment is performed. [0004] A gate insulating layer 3 and a gate 4 are formed on the substrate 1, wherein the gate insulating layer 3 is generally silicon oxide, and the gate 4 is a polysilicon gate or a metal gate, such as figure 2 shown. [0005] Ion implantation is performed on the substrate 1 on both sides of the gate 4...

AI Technical Summary

Problems solved by technology

[0008] With the shortening of the gate length of MOS devices in the semiconductor manufacturing process, the short channel effect of the MOS devices manufactured by the above process is continuously enhanced, and the leakage current is getting larger and larger, correspondingly leading to more and more power consumption, thereby shortening the The standby time of the produced electronic products

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