MOS tube and its forming method

Abstract

Disclosed are a MOS transistor and a forming method thereof. The forming method of the MOS transistor includes: providing a semiconductor substrate; forming a voltage control layer covering the semiconductor substrate and an epitaxial intrinsic layer covering the voltage control layer; forming a first gate structure on the surface of the epitaxial intrinsic layer and pseudo-sidewalls on two sides of the first gate structure; using the first gate structure and the pseudo-sidewalls as masks to dope in the epitaxial intrinsic layer to form a source / drain area; after the source / drain area forms, forming an insulating layer level to the first gate structure and the pseudo-sidewalls; after forming the insulating layer, removing the pseudo-sidewalls to form a first opening exposed out of the surface of the epitaxial intrinsic layer; doping ions into the epitaxial intrinsic layer through the first opening to form an anti-diffusion layer; forming a sidewall in the first opening. The surfaces of the sidewalls are level to the surface of the insulating layer. The formed MOS transistor is low in threshold voltage, heat carrier effect is eliminated, and the MOS transistor is stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a MOS tube and a forming method thereof. Background technique [0002] The forming method of the MOS tube in the prior art includes: [0003] Please refer to figure 1 , providing a semiconductor substrate 100, the surface of the semiconductor substrate 100 is covered with an insulating film 101, the surface of the insulating film 101 is covered with a polysilicon film 103, and the surface of the polysilicon film 103 has a photoresist layer 105; [0004] Please refer to figure 2 , using the photoresist layer 105 as a mask to etch the polysilicon film and insulating film until the semiconductor substrate 100 is exposed, forming a polysilicon layer 103a and an insulating layer 101a, and the polysilicon layer 103a is located on the insulating layer 101a surface; [0005] Please refer to image 3 After the insulating layer 101 a and the polysilicon layer 103 ...

AI Technical Summary

Problems solved by technology

[0007] However, the threshold voltage of the MOS tube formed by the prior art is relatively high, and the performance of the MOS tube still needs to be improved

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