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Late in-situ doped silicon germanium bonding for pmos devices

A silicon germanium and silicon nitride technology, applied in the field of ultra-low power technology, can solve problems such as lack of performance and low hole mobility

Active Publication Date: 2016-12-07
GLOBALFOUNDRIES SINGAPORE PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, to date 28SLP processes have not included embedded source / drain stressors such as SiGe in the p-active source / drain regions, and thus due to lower hole mobility efficiency and lack of efficiency

Method used

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  • Late in-situ doped silicon germanium bonding for pmos devices
  • Late in-situ doped silicon germanium bonding for pmos devices
  • Late in-situ doped silicon germanium bonding for pmos devices

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Embodiment Construction

[0019] In the following description, for purposes of explanation, various specific details are set forth in order to provide a thorough understanding of the exemplary embodiments. It may be evident, however, that the exemplary embodiments may be practiced without these specific details, or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram representation in order to avoid unnecessarily obscuring the exemplary embodiments. In addition, unless otherwise specified, it should be understood that all numerals used in the specification and drawings represent numerical properties of quantities, ratios, components, reaction conditions, and the like. In all instances, the term "about" can be modified.

[0020] The present invention addresses and solves the current problem of insufficient cladding of gate first HKMG with the formation of embedded SiGe source / drain regions in PMOS devices. According to the disclosed embodimen...

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Abstract

The present invention relates to late in-situ doped silicon germanium bonding for PMOS devices. Embodiments include forming first and second high-k metal gate stacks on the substrate, forming nitride liners and oxide spacers on each of the first and second high-k metal gates performing halo / extension implants on each side of each of the first and second high-k metal gate gate stacks, forming oxide liners and nitride spacers on each of the first and second On the oxide spacer of two high-k metal gate stacks; forming deep source / drain regions on opposite sides of the second high-k metal gate stack; forming oxide hard masking the second high-k metal gate stack; forming embedded silicon germanium on the opposite side of the first high-k metal gate stack; and removing the oxide hard mask.

Description

technical field [0001] The present invention relates to a high-k metal gate (HKMG) semiconductor device with embedded silicon germanium (SiGe) source / drain regions. The present invention is particularly suitable for 28nm super-low-power (28nm super-low-power, 28SLP) technology. Background technique [0002] In the current mobile / multimedia market, there is a huge demand for long standby time, specifically, low leakage products. The 28SLP process was originally designed to meet this requirement. However, there is also a need for high performance with low power consumption. Drives for high performance require high-speed operation of microelectronic components requiring high drive currents. Typically, increased structural and doping parameters that tend to provide the required drive current will adversely affect leakage current. High-k metal gate (HKMG) electrodes are developed to improve driving current by reducing polysilicon depletion. [0003] In modern CMOS technology...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/336H01L21/8238
CPCH01L21/823807H01L21/823814H01L21/823864H01L21/26513H01L29/6656H01L29/6659H01L29/66636H01L29/7833H01L29/7834H01L29/0847H01L21/2658H01L27/088H01L27/0922H01L29/1054H01L29/458H01L29/4925H01L29/7848
Inventor J·亨治尔S·Y·翁S·弗莱克豪斯基T·沙伊普
Owner GLOBALFOUNDRIES SINGAPORE PTE LTD
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