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An asymmetric ldmos process deviation monitoring structure and its manufacturing method

A process deviation, asymmetric technology, applied in semiconductor/solid state device manufacturing, transistors, electrical components, etc., can solve problems such as deviation

Active Publication Date: 2016-04-13
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, there is a monitoring structure for the deviation of the well region in the process production, but this monitoring structure cannot directly reflect the difference in the performance of asymmetric LDMOS devices, and cannot directly put forward the monitoring requirements for the deviation in the process

Method used

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  • An asymmetric ldmos process deviation monitoring structure and its manufacturing method
  • An asymmetric ldmos process deviation monitoring structure and its manufacturing method

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Embodiment Construction

[0030] Such as figure 1 As shown, the monitoring structure of the process deviation of the asymmetric LDMOS device of the present invention includes: two asymmetric LDMOS devices with the same layout design;

[0031] The asymmetric LDMOS device includes: an N-type epitaxial layer formed on a P-type substrate, an N-type buried layer and a P-type buried layer in the N-type epitaxial layer, a P-type well region 2 and a P-type well region 1 in the N-type buried layer N-type well region 3, field regions 4 formed on both sides of N-type well region 3, N-type heavily doped region 5 formed in N-type well region 3, formed in P-type well region 2 (two LDMOS devices share P The P-type heavily doped region 6 and the N-type heavily doped region 5 in the well), and the polysilicon gate 7 formed above the field region 4 and the P-type well region 22;

[0032] Two asymmetric LDMOS devices share a substrate lead-out, and the sources 8 of the two asymmetric LDMOS are connected to the common su...

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Abstract

The invention discloses an asymmetric LDMOS process deviation monitoring structure. The asymmetric LDMOS process deviation monitoring structure comprises two asymmetric LDMOS components which are complete same in layout design, which are distributed in one row and which share a P-type well region. The P-type well region is provided with N-type heavily doped regions and P-type heavily doped regions at intervals. The two asymmetric LDMOS components share one liner output end, the source electrodes of the two asymmetric LDMOS components are connected to output ends of the shared liner through metal silicide, contacting holes and metal leads. Asymmetric LDMOS grid electrodes serve as the output ends, and asymmetric LDMOS drain electrodes serve as the output ends. The invention further discloses a manufacturing method of the asymmetric LDMOS process deviation monitoring structure. According to the asymmetric LDMOS process deviation monitoring structure, the differences of electrical performances between the asymmetric LDMOS components in same design can be measured, critical level deviation in process can be determined. The deviation of the asymmetric LDMOS components can be reduced by the method of adjusting the process, and performances and in-plane uniformity can be improved.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a monitoring structure for asymmetry LDMOS process deviation. The invention also relates to a manufacturing method of an asymmetric LDMOS process deviation monitoring structure. Background technique [0002] BCD technology is widely used in various power management, power amplifier and other products. The core device in this type of product is asymmetric LDMOS (laterally diffused metal oxide semiconductor). The performance of asymmetric LDMOS devices directly determines the performance of this type of product. Product performance and cost. The performance of asymmetric LDMOS depends largely on process control. The performance of a typical asymmetric LDMOS device is determined by the device's channel length (LCH), channel accumulation region (LA), and gate field plate. Since the channel of an asymmetric LDMOS device is mainly determined by the well region, and the in-...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/088H01L21/8234
CPCH01L22/34
Inventor 仲志华
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP