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Bus framework for multiple processors to process applications concurrently

A parallel processing and multi-processor technology, applied in the direction of electrical digital data processing, instruments, etc., can solve problems such as bus competition, achieve the effects of weakening competition bottlenecks, improving communication efficiency, and meeting high real-time requirements

Inactive Publication Date: 2014-01-08
XUJI GRP +2
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  • Abstract
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  • Claims
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AI Technical Summary

Problems solved by technology

[0005] The purpose of the present invention is to provide a bus architecture for multiprocessor parallel processing applications to solve the bus contention problem existing in the existing multiprocessor parallel processing applications

Method used

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  • Bus framework for multiple processors to process applications concurrently
  • Bus framework for multiple processors to process applications concurrently
  • Bus framework for multiple processors to process applications concurrently

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Embodiment Construction

[0014] 1. Bus architecture for multiprocessor parallel processing applications: segmented parallelism

[0015] like figure 1 As shown, in the bus architecture for multiprocessor parallel processing applications, the bus is N sections of sub-buses set in parallel, each section of sub-buses is connected to at least one CPU plug-in, N is a natural number greater than or equal to 2, and the setting of N value is related to the CPU board , The number of I / O boards is related, where N is set to 3.

[0016] The traditional shared parallel bus is segmented (divided into 3 segments), and each segment is a fully functional parallel bus backplane structure, forming a segmented multi-bus architecture from the perspective of the overall chassis.

[0017] In the application of HVDC power transmission system, it is most common that there are less than or equal to 3 CPUs in one chassis. Then, if a high-speed parallel bus is divided into three parallel buses, most of the application needs wi...

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Abstract

The invention relates to a bus framework for multiple processors to process applications concurrently. According to a bus, N sections of sub-buses are arranged in parallel, each section of sub-bus is connected with at least one CPU plug-in, N is a natural number and is larger than or equal to 2, the bus is segmented to provide a plurality of parallel buses (namely more usable resources are provided), and competition of a signal common bus is converted into competition of segmented buses. Due to the fact that the number of the CPUs of the segmented buses is reduced, the load condition of the segmented buses is bettered. The segmented buses are mutually independent and do not affect one another, so that the competition bottleneck of bus resources is obviously relieved due to the multiple segmented buses compared with a traditional single parallel bus structure. The segmented multi-bus structure provides a more reasonable choice for configuration optimization of a direct current power transmission application function in a machine case.

Description

technical field [0001] The invention relates to a bus architecture for multiprocessor parallel processing applications. Background technique [0002] The control and protection platform is the core equipment of the secondary side of the converter station of the direct current transmission project, and is the nerve center of the direct current transmission control and protection system. In HVDC power transmission projects, the control and protection platform is used in many occasions such as station control, pole control, valve group control, AC and DC protection, etc. To sum up their common characteristics, they are all multi-processor parallel processing applications, that is, according to the complexity of the application, several CPUs are configured in one chassis, and each CPU is combined with the corresponding peripheral I / O plug-in to form multiple CPUs with specific functions. processing collection. But in the traditional design, all CPUs and peripheral plug-ins in ...

Claims

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Application Information

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IPC IPC(8): G06F13/36
Inventor 李延龙蒋大海李宝香张宝华吴述超魏民权侯林杰
Owner XUJI GRP
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