SRAM (Static Random Access Memory) cell as well as circuit and method of forming same

Abstract

The invention relates to an SRAM (Static Random Access Memory) cell as well as a circuit and a method of forming the same, wherein the SRAM cell comprises a first PMOS (P-channel Metal Oxide Semiconductor) transistor, a second PMOS transistor, a first NMOS (N-channel Metal Oxide Semiconductor) transistor, a second NMOS transistor, a first transfer transistor and a second transfer transistor; the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor form a bistable circuit, and defects exit in the gate dielectric layers, close to source electrodes, of the first transfer transistor and second transfer transistor, and are formed by virtue of injecting hot carriers. During a reading operation, the saturation source drain current values of the first transfer transistor and the second transfer transistor are reduced, so that the reading margin of the SRAM cell is improved, and the writing margin of the SRAM cell is not influenced.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to an SRAM storage unit, a circuit for forming the SRAM storage unit and a forming method. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] figure 1 It is a schematic diagram of the circuit structure of the storage unit of the existing 6T structure SRAM memory, the storage unit includes: a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, and a third NMOS transistor N3 and a fourth NMOS transistor N4. [0004] The first PMOS transistor P1, the second PMOS transistor P2, the first NMOS transistor N1, and the second NMOS transi...

AI Technical Summary

Problems solved by technology

[0010] However, as the process node of the CMOS process decreases, the operating voltage decreases, and random doping leads to an increase in threshold voltage variation, which poses challenges to the read stability of SRAM.

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