Semiconductor device manufacturing method

Abstract

Provided is a manufacturing method for a semiconductor device. The method comprises: forming a stacked gate structure on a substrate; depositing a dielectric material layer on the substrate and the stacked gate structure; performing main etching to etch the dielectric material layer so as to form a side wall, and leaving residues of the dielectric material layer on the substrate; and performing over-etching to remove the residues of the dielectric material layer. According to the provided manufacturing method for the semiconductor device, instead of using a silicon oxide etching barrier layer, a two-step etching by using a fluorocarbon-based gas is performed so that while the damage to the substrate is reduced, the process complexity is also reduced, and besides, the threshold voltage can be optimized, the EoT can be effectively reduced, and the gate-control capability and the drive current can be increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a sidewall etching method. Background technique [0002] In the manufacturing of very large scale integrated circuits, dielectric spacers need to be fabricated before the lightly doped drain (LDD) implantation process to prevent a larger dose of source and drain implants from being too close to the channel to cause the source and drain to pass through, resulting in device failure And the yield rate is reduced. [0003] Currently used in the mainstream 65nm or even 45nm sidewall manufacturing process: before the lightly doped drain (LDD) implantation process, first deposit or thermally grow a layer of silicon dioxide film, such as rapid thermal oxidation (RTO) growth The silicon dioxide on the left and right is used as an etching stop layer for the subsequent silicon nitride material to protect the substrate, especially the interface between...

AI Technical Summary

Problems solved by technology

[0005] However, when the above-mentioned traditional silicon oxide first and then silicon nitride composite sidewall is applied to the high-k-metal gate structure, since the SiN sidewall must be grown by RTO to form SiO 2 layer, the dummy gate, which is usually polysilicon, will also partially react during this process, especially at the interface between the dummy gate and the substrate Si, thereby increasing the thickness of the gate oxide layer, if this is not considered parasitic SiO 2 layer without taking additional etching, leaving an additional thickness of SiO below the dummy gate stack 2 layer will reduce the overall dielectric constant of the gate insulating layer mainly composed of high-K materials, which will increase the EoT and ultimately reduce the gate control capability and drive current

[0006] In summary, when the traditional SiN sidewall etching method is applied to the high-k-metal gate structure of the gate-last process, there is a defect of increased EoT, and it is difficult to effectively improve the gate control capability and drive current.

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