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Low-power-consumption divide-by-two frequency divider with gating function

A two-frequency divider, low-power technology, applied in the field of low-power divide-by-two frequency dividers, can solve problems such as small layout area

Active Publication Date: 2014-01-22
南京中科微电子有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

figure 2 Shown is a multi-way switch based on current mode logic in the prior art. In order to work at several GHz or more and have corresponding amplification capabilities, the power consumption of this multi-way switch is at least 1mA. In addition, the multi-way switch Due to the high frequency of operation, the size of the tube and the layout of the layout are very particular. This circuit will occupy a large layout area.

Method used

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  • Low-power-consumption divide-by-two frequency divider with gating function
  • Low-power-consumption divide-by-two frequency divider with gating function
  • Low-power-consumption divide-by-two frequency divider with gating function

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Embodiment 1

[0028] like Figure 4 As shown, the present invention provides a low-power divider by two frequency divider with a gating function, which includes a quadrature local oscillator signal output terminal, a clock signal gating control terminal and two pairs of clock signal input terminals; The two pairs of clock signal input terminals respectively receive the high-band clock signal and the low-band clock signal. The local oscillator signal output terminal outputs a quadrature local oscillator signal.

[0029] like Figure 5As shown, in this embodiment, the frequency divider includes two identical D latches, one master D latch and one slave D latch, each of the two D latches The D latch includes a pair of differential data input terminals D and DN, a clock signal gating control terminal S, a pair of differential output terminals Q and QN, and two pairs of differential clock signal input terminals CKA_P, CKA_N, CKB_P and CKB_N. The clock signal strobe control end of the master D ...

Embodiment 2

[0037] like Figure 7 As shown, the difference between this embodiment and the above-mentioned embodiment 1 is that the load resistance includes a field effect transistor M19 and a field effect transistor M20 working in the linear resistance region, and the source of the field effect transistor M19 is connected to the field effect transistor M20. The source of the transistor M20 is connected to the power supply AVDD, the gate of the field effect transistor M19 is grounded to the gate of the field effect transistor M20, and the drain of the field effect transistor M19 is electrically connected to the drain of the field effect transistor M1, The drain of the field effect transistor M20 is electrically connected to the drain of the field effect transistor M2.

[0038] Since the maximum operating frequency of the current mode logic divider by two is mainly determined by the RC delay composed of the load resistance and the load capacitance of the divider by two. Load capacitance c...

Embodiment 3

[0040] like Figure 8 As shown, the difference between this embodiment and the above-mentioned embodiment 2 is that the load resistor also includes a field effect transistor M23 and a field effect transistor M24, and the source and drain of the field effect transistor M23 are connected across the field effect transistor Between M19 and the field effect transistor M20, the source and drain of the field effect transistor M24 are connected between the field effect transistor M19 and the field effect transistor M20, and the gate of the field effect transistor M23 The gate of the field effect transistor M7 is electrically connected, and the gate of the field effect transistor M24 is electrically connected to the gate of the field effect transistor M8.

[0041] In this embodiment, on the basis of using field effect transistors as active resistors instead of load resistors, clock-controlled field effect transistors are added across the two ends of the load resistors. Its working pri...

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PUM

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Abstract

The invention provides a low-power-consumption divide-by-two frequency divider with a gating function. The low-power-consumption divide-by-two frequency divider comprises an orthogonal local oscillator signal output end, a clock signal gating control end and two pairs of clock signal input ends; and after the frequency divider is used for gating two clock signals input by the clock signal input ends, the two clock signals are subjected to divide-by-two frequency division to output orthogonal local oscillator signals by the orthogonal local oscillator signal output end. Two D latches are adopted and are connected in a master-slave relation and a selective control function of the D latches is utilized so as to meet the gating requirements and enable the divide-by-two frequency divider to realize the requirements of outputting oscillator signals with larger bandwidth frequencies. Meanwhile, equivalently an alternative multi-path switch is embedded into the divide-by-two frequency divider so that consumed current is the current of the divide-by-two frequency divider, the current consumed by the multi-path switch is lacked and the power consumption is reduced.

Description

technical field [0001] The invention relates to the field of communication control, in particular to a low-power divider by two with a gating function. Background technique [0002] As we all know, the local oscillator signal is the key to spectrum shifting in radio frequency microwave communication. The receiving and transmitting signals are the key to spectrum shifting. When the digital signal is transmitted, it needs to be converted into a digital signal and then mixed with the local oscillator signal to the radio frequency before being transmitted. The same is true in When receiving, the radio frequency that is expected to be received must be amplified, and then the local oscillator signal is mixed and amplified before it can be converted into a digital signal and handed over to the back-end for processing. Generally, the low-IF and zero-IF schemes of the receiver are better. [0003] With the high-speed development of communication technology, higher requirements are pu...

Claims

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Application Information

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IPC IPC(8): H03K21/00
Inventor 樊晓华
Owner 南京中科微电子有限公司