Low-power-consumption divide-by-two frequency divider with gating function
A two-frequency divider, low-power technology, applied in the field of low-power divide-by-two frequency dividers, can solve problems such as small layout area
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Embodiment 1
[0028] like Figure 4 As shown, the present invention provides a low-power divider by two frequency divider with a gating function, which includes a quadrature local oscillator signal output terminal, a clock signal gating control terminal and two pairs of clock signal input terminals; The two pairs of clock signal input terminals respectively receive the high-band clock signal and the low-band clock signal. The local oscillator signal output terminal outputs a quadrature local oscillator signal.
[0029] like Figure 5As shown, in this embodiment, the frequency divider includes two identical D latches, one master D latch and one slave D latch, each of the two D latches The D latch includes a pair of differential data input terminals D and DN, a clock signal gating control terminal S, a pair of differential output terminals Q and QN, and two pairs of differential clock signal input terminals CKA_P, CKA_N, CKB_P and CKB_N. The clock signal strobe control end of the master D ...
Embodiment 2
[0037] like Figure 7 As shown, the difference between this embodiment and the above-mentioned embodiment 1 is that the load resistance includes a field effect transistor M19 and a field effect transistor M20 working in the linear resistance region, and the source of the field effect transistor M19 is connected to the field effect transistor M20. The source of the transistor M20 is connected to the power supply AVDD, the gate of the field effect transistor M19 is grounded to the gate of the field effect transistor M20, and the drain of the field effect transistor M19 is electrically connected to the drain of the field effect transistor M1, The drain of the field effect transistor M20 is electrically connected to the drain of the field effect transistor M2.
[0038] Since the maximum operating frequency of the current mode logic divider by two is mainly determined by the RC delay composed of the load resistance and the load capacitance of the divider by two. Load capacitance c...
Embodiment 3
[0040] like Figure 8 As shown, the difference between this embodiment and the above-mentioned embodiment 2 is that the load resistor also includes a field effect transistor M23 and a field effect transistor M24, and the source and drain of the field effect transistor M23 are connected across the field effect transistor Between M19 and the field effect transistor M20, the source and drain of the field effect transistor M24 are connected between the field effect transistor M19 and the field effect transistor M20, and the gate of the field effect transistor M23 The gate of the field effect transistor M7 is electrically connected, and the gate of the field effect transistor M24 is electrically connected to the gate of the field effect transistor M8.
[0041] In this embodiment, on the basis of using field effect transistors as active resistors instead of load resistors, clock-controlled field effect transistors are added across the two ends of the load resistors. Its working pri...
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