Array substrate, preparation method thereof and display device

Abstract

The invention discloses a preparation method of an array substrate. The preparation method of the array substrate comprises the steps that the surface of a substrate is coated with negative photoresist; the back face of the substrate is exposed, and then development is conducted by a negative photoresist developing solution; a layer of amorphous ITO is deposited on the substrate, and then the negative photoresist is peeled off; an annealing process is conducted. The invention further discloses the array substrate and a display device. According to the array substrate, the preparation method of the array substrate and the display device, panel imaging quality can be improved, and pixel defects cannot be caused.

Description

technical field [0001] The invention relates to the field of liquid crystal display, in particular to an array substrate, a preparation method thereof, and a display device. Background technique [0002] Advanced Super Dimension Switch technology (ADvanced Super Dimension Switch, AD-SDS, referred to as ADS), through the electric field generated by the edge of the slit electrode in the same plane and the electric field generated between the slit electrode layer and the plate electrode layer to form a multi-dimensional electric field, All oriented liquid crystal molecules between the slit electrodes in the liquid crystal cell and directly above the electrodes can be rotated, thereby improving the working efficiency of the liquid crystal and increasing the light transmission efficiency. Advanced ultra-dimensional field conversion technology can improve the picture quality of TFT-LCD products, with high resolution, high transmittance, low power consumption, wide viewing angle, h...

AI Technical Summary

Problems solved by technology

However, when the deposition thickness of the amorphous ITO common electrode is increased to about 700 angstroms, due to the difference in the deposition environment between the center and edge of the glass substrate, the amorphous ITO at the edge of the glass substrate begins to polycrystallize, while the polycrystalline ITO and amorphous ITO The etching speed varies greatly. Therefore, in the etching process, due to the slow etching speed of the edge polycrystalline ITO, the edge amorphous ITO may remain, so that the pixels are connected by the residual amorphous ITO, resulting in poor panel pixels. Therefore, , the thickness of the ITO common electrode cannot be increased simply by increasing the deposition thickness of amorphous ITO in the amorphous ITO common electrode patterning process

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