Time clock synchronizing method and device

Abstract

The embodiment of the invention discloses a time clock synchronizing method and device. The method comprises the steps of starting a counter; calculating the sum of a value and an accumulated value of the counter in the current time clock period as a comparison value; judging whether the comparison value in the current time clock period is larger than a threshold value; if the comparison value is larger than the threshold value, giving the difference value of the comparison value and the threshold value to the counter as the value of the counter in the next time clock period, taking the time clock signal subjected to negation and stored in a register in the current time clock period as the time clock signal stored in the register in the next time clock period and as the synchronous time clock signal in the current time clock period for outputting; if the comparison value is smaller than or equal to the threshold value, taking the comparison value as the value of the counter in the next time cock period and taking the time clock signal stored in the register in the current time clock period as the synchronous time clock signal in the current time clock period for outputting. The scheme provided by the embodiment of the invention can realize time clock synchronization and the phase following with low cost and high precision.

Description

technical field [0001] The present invention relates to the technical field of communication, and more specifically, to a clock synchronization method and device. Background technique [0002] At present, in order to ensure clock synchronization between network devices, a PLL (Phase Locked Loop, phase locked loop) technology is usually used for implementation. For example, a TDM PON (Time Division Multiplexing Passive Optical Network, Time Division Multiplexing Passive Optical Network) system is a clock synchronization system, in which network devices in the system use PLL technology to achieve clock synchronization. [0003] There are many types of PLLs, mainly including integer frequency dividers, fractional frequency dividers, and decimal frequency dividers. Since the use of the integer frequency divider and the fractional frequency divider has many restrictions, the fractional frequency divider is usually used to implement clock synchronization between network devices i...

AI Technical Summary

Problems solved by technology

If there is a certain frequency deviation between the clock of the voice terminal equipment and the clock of the network equipment, it may cause problems such as the inability to realize voice synchronization, so the synchronization performance of the telephone voice system is reduced

Images