A method for reducing errors in the observation of wafers by an electron microscope
An electron microscope and defect technology, applied in the direction of circuit, electrical components, semiconductor/solid-state device testing/measurement, etc., can solve the problems of reducing the accuracy of defect observation and inability to complete defect detection, so as to ensure accuracy and reduce defect errors , the effect of eliminating errors
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[0040] The specific embodiment of the present invention will be further described below in conjunction with accompanying drawing:
[0041] Figure 7 It is a schematic flow chart of an embodiment of a method for reducing the error of electron microscope observation of wafer defects in the present invention, Figure 8 for Figure 7 Schematic diagram of the distribution of chips on the wafer and the starting position of the chips defined by the electron microscope; Figure 7-8 As shown, a method for reducing the error of electron microscope observation of wafer defects, including:
[0042] First, a wafer for defect detection is provided, on which a plurality of chip structures (such as multiple chips distributed in an array, etc.) are provided.
[0043]Secondly, use an electron microscope to define the parameter information on the above wafer, which includes the starting position of the chip, the size of each chip, the distance between two adjacent chips, and the position of e...
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