Preparation method for SGOI (silicon germanium on insulator) structure

Abstract

The invention provides a preparation method for an SGOI (silicon germanium on insulator) structure. The preparation method at least comprises a first step of providing an SOI substrate, and enabling a single crystal SiGe layer to be subject to epitaxial growth on the surface of top layer silicon; a second step of forming a Si cap layer on the surface of the single crystal SiGe layer; a third step of performing ion implantation on the front of the Si cap layer, and enabling the implantation depth to reach the inside of the top layer silicon; a fourth step of performing germanium concentration on the structure obtained in the third step, and forming a laminated structure which sequentially comprises a back substrate, a buried oxide layer, a preset Ge concentration SiGe layer and a SiO2 layer from bottom to top; and a fifth step of etching off the SiO2 layer on the surface of the laminated structure so as to obtain the SGOI structure. The SGOI structure high in quality and Ge concentration is manufactured by combination with an ion implantation technology and a germanium concentration process, and the ion implantation weakens lattice mismatch between the top layer silicon and the SiGe layer; along with the annealing process, dislocation rings interact in the longitudinal direction and offset each other, stress is released, and accordingly the penetrating dislocation density in the finally obtained SGOI structure is greatly reduced.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing and relates to a preparation method of an SGOI structure. Background technique [0002] SOI (Silicon-On-Insulator, silicon on insulating substrate) technology introduces a buried oxide layer between the top silicon and the back substrate. By forming a semiconductor thin film on an insulator, the SOI material has the incomparable advantages of bulk silicon: it can realize the dielectric isolation of components in integrated circuits, and completely eliminate the parasitic latch effect in bulk silicon CMOS circuits; The integrated circuit also has the advantages of small parasitic capacitance, high integration density, fast speed, simple process, small short channel effect, and is especially suitable for low-voltage and low-power circuits. Therefore, it can be said that SOI will likely become a deep submicron low-voltage , The mainstream technology of low-power integrated circuits. Howev...

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing an SGOI structure, which is used to solve the problems of high threading dislocation density and poor quality in the SGOI structure prepared in the prior art

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