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Formation method of package structure

A technology of packaging structure and plastic packaging layer, which is applied in the manufacturing of electrical components, electric solid-state devices, semiconductor/solid-state devices, etc.

Active Publication Date: 2016-04-20
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Existing lead frame packages can only be packaged for a single semiconductor chip and lead frame, and the packaging efficiency is low

Method used

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  • Formation method of package structure
  • Formation method of package structure
  • Formation method of package structure

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Experimental program
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Embodiment Construction

[0023] When encapsulating existing leadframes, please refer to the figure 1 First, the wafer needs to be cut to form semiconductor chips 14 one by one, and then metal wires 17 are formed through a wire bonding process. The metal wires 17 connect the pads 15 on the semiconductor chips 14 with the surrounding pins 16, and finally pass The plastic encapsulation material 18 encapsulates the semiconductor chip 14 and the pin 16. The existing packaging process can only realize the packaging of a single semiconductor chip and pin, and the encapsulation efficiency is low. In addition, the pins 16 are arranged around the semiconductor chip 14, and the pads 15 on the semiconductor chip 14 need to be electrically connected to the surrounding pins 16 through metal wires 17, so that the volume occupied by the entire packaging structure is relatively large. , which is not conducive to the improvement of the integration degree of the packaging structure.

[0024]The invention provides a met...

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Abstract

The invention discloses a packaging structure forming method. The forming method comprises the following steps: a lead frame is provided, wherein the lead frame comprises a first surface and a second surface which is opposite to the first surface, the lead frame is provided with a plurality of bearing units which are arranged in a matrix manner and medium-strength ribs for fixing the bearing units, each bearing unit comprises a plurality of discrete pins, and an opening is formed between every two neighboring pins; first metal bumps are formed on first surfaces of the pins; a pre-packaged panel is provided, wherein the pre-packaged panel comprises a first plastic packaged layer, a plurality of integrated units are arranged in the first plastic packaged layer, at least one semiconductor chip is arranged in each integrated unit, surfaces of the semiconductor chips are provided with a plurality of bonding pads, bonding pads on the semiconductor chips are exposed out from the first plastic packaged layer, the bonding pads are provided with second metal bumps, and a solder layer is formed on the second metal bumps; and the pre-packaged panel is arranged on the first surface of the lead frame in a flipping manner, and the second metal bumps on the semiconductor chips and the first metal bumps on the pins are soldered together. According to the packaging structure of the invention, the integration level is improved.

Description

technical field [0001] The invention relates to the field of semiconductor packaging, in particular to a method for forming a packaging structure. Background technique [0002] With the development of electronic products such as mobile phones and notebook computers towards miniaturization, portable, ultra-thin, multimedia and low-cost to meet the needs of the public, high-density, high-performance, high-reliability and low-cost packaging forms and their Assembly technology has been rapidly developed. Compared with expensive BGA (BallGridArray) and other packaging forms, new packaging technologies that have developed rapidly in recent years, such as Quad Flat No-lead QFN (QuadFlatNo-leadPackage) packaging, due to their good thermal performance and electrical performance, small size Many advantages, such as low cost and high productivity, have triggered a new revolution in the field of microelectronic packaging technology. [0003] figure 1 It is a structural schematic diag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/50
CPCH01L21/4885H01L21/50H01L24/81H01L2224/81H01L2224/04105H01L2224/11H01L2224/12105H01L2224/16245H01L2224/48091H01L2224/48247H01L2224/95H01L2224/96H01L2924/181H01L2924/18165H01L2924/3511H01L2924/00014H01L2924/00012
Inventor 陶玉娟刘培生
Owner NANTONG FUJITSU MICROELECTRONICS