Coarse granularity dynamic reconfigurable data integration and control unit structure

Abstract

The invention discloses a coarse granularity dynamic reconfigurable data integration and control unit structure. A data stream control module comprises a vector loading module, a vector phase shift module and an unpacking and distribution module. The three modules achieve multi-level composite two-stage flow lines through a double-buffering register, and achieve synchronization of the flow lines through hardware handshake. The vector loading module achieves access to different data address spaces through dynamic configuration allocation, and finishes data loading from a memory to a vector data register file. The vector phase shift module achieves shift, splicing and other operations of data stream in a dynamic reconfigurable allocation mode, and output data are written into a vector phase register file. The unpacking and distribution module achieves distribution of the register data through allocation, and meets the requirement of an array for concurrent input of calculation data. The coarse granularity dynamic reconfigurable data integration and control unit structure effectively solves the non-aligned access and data integration problems in the data loading process.

Description

technical field [0001] The invention relates to a coarse-grained dynamic reconfigurable data regularization control unit structure, which belongs to the embedded reconfigurable design technology. Background technique [0002] Reconfigurable computing is a computing method that combines the flexibility of software and the efficiency of hardware. For example, field programmable logic gate array is a specific example of reconfigurable computing applications. The difference between it and ordinary microprocessors is that it can not only change the control flow, but also change the structure of the data path. It has the advantages of high performance, low hardware overhead and power consumption, good flexibility and good scalability. At present, it is mainly used in computing-intensive algorithms such as media processing, pattern recognition, and baseband processing. As embedded processors generally require shortening the design cycle, reducing design and development costs, and ...

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Problems solved by technology

Such a design simplifies the data routing path, but the reconfigurable computing unit for access also occupies computing resources, especially the data access of the reconfigurable computing unit will cause the entire array computing pipeline to be blocked, resulting in computing performance being affected. limit

Although the memory access overhead can be effectively hidden by exploring the prefetch and reuse of data, it is still affected by data parallelism and cannot use the data dependencies between multiple calculations to obtain better execution performance of data parallelism.

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