Formal verification method for sequencing specification of FPGA (field programmable gate array) combinatorial logic system

Abstract

The invention discloses a formal verification method for a sequencing specification of an FPGA (field programmable gate array) combinatorial logic system. The formal verification method comprises the following steps of (1) obtaining a VHDL (very-high-speed integrated circuit hardware description language) procedure according to an operation sequencing specification of the FPGA combinatorial logic system; (2) establishing a Petri net model according to the VHDL procedure; (3) establishing a reachability graph according to the Petri net model; (4) pitching on all stable gate circuit output states in the reachability graph; (5) generating a control specification comprising a logical formula for calculating tree tense according to the operation sequencing specification of the FPGA combinatory logic system; and (6) detecting whether the stable gate circuit output states in the reachability graph meet the control specification or not, determining that the states are mistaken if the stable gate circuit output states in the reachability graph do not meet the control specification, positioning mistaken statements in the VHDL procedure according to excitable changes generating the mistaken states, and determining that the VHDL procedure meets the design requirements if all the states meet the control specification. The formal verification method for the sequencing specification of the FPGA combinatorial logic system is rigorous and complete in logicality and low in complexity.

Description

technical field [0001] The invention relates to a method for verifying sequence specifications of an FPGA combined logic system, in particular to a formalized method for verifying the sequence specifications of an FPGA combined logic system. Background technique [0002] Field Programmable Gate Array (FPGA Field-Programmable Gate Array) is the product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. Its appearance has a profound impact on digital system design. FPGA is widely used in communications, Military, medical, automotive electronics, industrial control, consumer products and other important fields. [0003] The current popular FPGA design method is to use VHDL or Verilog language as the hardware input description, and then map the hardware description language to the logic circuit through the synthesis of the synthesizer, and then use the tools provided by the FPGA manufacturer to carry out the wiring layout, and the logic gene...

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Problems solved by technology

However, the Petri net describes a more complex concurrent system than the FPGA system. In theory, as long as the transition meets the excitation conditions, it can be excited. Since there is no sequence of excitation, it is easy to cause an infinite loop. The output state of the gate circuit is generated when the logic operation of the gate circuit is performed. At the same time, the possible input quantity is also constantly changing, so many intermediate states that are caused by the nature of the Petri net itself and have nothing to do with the actual system will be generated. come with great difficulty

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