Semiconductor device and method for preparing same

Abstract

The present invention relates to a semiconductor device and a method for preparing the same. The method comprises the steps of providing a semiconductor substrate, wherein the substrate comprises a basement, an oxide layer and a semiconductor material layer; forming a patterned hard mask layer on the substrate, wherein the hard mask layer comprises a plurality of openings; etching the semiconductor material layer by taking the hard mask layer as a mask to form a sigma-shaped groove; epitaxially growing a SiGe layer in the groove to form a fin; removing the hard mask layer to expose the semiconductor material layer; etching the semiconductor material layer to expose the fin. According to the method of the present invention, the hard mask layer is formed on a SOI substrate, and then the sigma-shaped groove is formed by controlling the etching conditions, then the SiGe layer is grown epitaxially to obtain the rhombic fin, and finally a gate all around (GAA) is formed, so that the lower surface of the fin is totally used as a groove area, a working current can be increased further, and the integration level and performance of the device are improved further.

Description

technical field [0001] The present invention relates to the field of semiconductors, and in particular, the present invention relates to a semiconductor device and a preparation method thereof. Background technique [0002] The improvement of integrated circuit performance is mainly achieved by continuously reducing the size of integrated circuit device to increase its speed. Currently, as the semiconductor industry has advanced to nanotechnology process nodes in pursuit of high device density, high performance, and low cost, especially as semiconductor device dimensions drop to 22nm or below, challenges from fabrication and design have led to 3D design Such as the development of fin field effect transistor (FinFET). [0003] Compared with the existing planar transistors, the FinFET device has more superior performance in channel control and reduction of shallow channel effects. The planar gate structure is arranged above the channel, while in the FinFET the gate It is arr...

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Problems solved by technology

[0005] In the prior art, the fins forming the gate all around (GAA) are mostly columnar, and the lower surface of the fins is not completely used as a channel region, so there is a limitation in increasing the operating current

[0006] Therefore, although there are gate all around (GAA) transistors in the prior art, the current fabrication methods and the obtained transistors have a relatively small operating current, and at the same time, as the size decreases, the integration degree is also affected, so that The performance of semiconductor devices is limited, so current fabrication methods need to be improved to eliminate the above problems

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