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A phase-change memory write acceleration method and system thereof

A technology of phase change memory and memory bank, which is applied in static memory, digital memory information, information storage, etc., and can solve the problems of slow SET operation speed and performance degradation of phase change memory

Active Publication Date: 2016-08-17
INST OF COMPUTING TECH CHINESE ACAD OF SCI
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  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0021] The technical problem to be solved by the present invention is to provide a phase-change memory write acceleration method and its system to overcome the problem in the prior art that the SET operation speed is too slow, which causes the performance of the entire phase-change memory to decline

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  • A phase-change memory write acceleration method and system thereof
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  • A phase-change memory write acceleration method and system thereof

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specific Embodiment 1

[0166] like Figure 13A , the initial state of the Partial-SET queue is: only one item contains the information of A, and there are three empty items. When B's write request is written according to the Partial-SET method, the corresponding Partial-SET queue is not full, and there is no item with the same address as B in the current queue, therefore, insert B into the Partial-SET queue, and B The time field of the item is initialized to zero. After performing this series of operations, the status of the Partial-SET queue is: two items are occupied, the value of the time domain of item A is the largest, and the value of the time domain of item B is the second, which is placed in the second item.

specific Embodiment 2

[0167] like Figure 13B , the initial state of the Partial-SET queue is: there are three items containing the information of A, B, and C respectively, the time domain values ​​of these three items decrease in turn, and there is one empty item. The write request of A chooses to use the pulse of Partial-SET to execute the write "1" operation. The item of A in the current queue already exists, so the item of A is deleted from the current position, and the new item of A is inserted at the end of the queue. At this time, the item of A The time domain value is zero. After executing this series of operations, the state of the Partial-SET queue is: there are items B, C, and A, and the values ​​of the time domains of these three items decrease in turn, and the value of the time domain of item B is the largest.

specific Embodiment 3

[0168] like Figure 13C , the initial state of the Partial-SET queue is: the information of A, B, and C is stored, and the value of the time domain decreases in turn, and the value of the time domain of A is the largest. The memory storage bank is in the idle state, the request queue status is empty, and the prediction result of the predictor is that the current memory storage bank idle interval is long, delete item A from the Partial-SET queue, and execute the corresponding row A in the phase change memory Compensation for SET operations. After executing this series of operations, the state of the Partial-SET queue is: there are items B and C, and the time domain values ​​of these two items decrease in turn, and the value of the time domain of item B is the largest. The state of row A in the phase change memory is a reliable complete SET state.

[0169] In summary, compared with the prior art, the write acceleration method of the phase change memory of the present invention...

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Abstract

The invention discloses a writing acceleration method for a phase change memory. The method comprises the steps of Partial-SET writing operation judgment and writing request execution, wherein in the step of Partial-SET writing operation judgment, the adopted writing pulse type of a current writing request in the phase change memory is determined as SET or Partial-SET pulse; in the step of writing request execution, quick Partial-SET writing acceleration of the phase change memory is realized by using a SET or Partial-SET method at different writing speeds of SET operation and RESET operation according to the writing pulse type. The invention also discloses a writing acceleration system for the phase change memory.

Description

technical field [0001] The invention relates to performance optimization of modern computer storage technology, in particular to a new type of non-volatile storage technology, that is, a phase-change memory, in particular to a phase-change memory write acceleration method and a system thereof. Background technique [0002] In recent decades, the main memory in the computer system has been using Dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) technology. However, as semiconductor manufacturing technology shrinks to below 20 nanometers, DRAM technology faces the problem of continuous shrinking process dimensions. Therefore, new storage technologies with outstanding scaling capabilities are receiving more and more attention. Among them, phase change memory (PhaseChange Memory, PCM) is considered to be the most important component of main memory. Compared with traditional DRAM technology, phase change memory technology not only has the advantages of non-volat...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/56
Inventor 李冰胡瑜单书畅李晓维
Owner INST OF COMPUTING TECH CHINESE ACAD OF SCI
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