37results about How to "Reduce write power consumption" patented technology

A multi-port SRAM with shared write bit-line architecture and selective read path for low power operation includes a first memory cell, a second memory cell, and a common switch set. The second memory cell makes use of the common switch set to share the A-port write bit-line and the B-port write bit-line with the first memory cell so as to reduce half write bit-line number and reduce the write current consumption caused by pre-charging the bit-line to VDD. It also provides a selective read path structure for read operation. Replacing the ground connection in the read port with a virtual VSS controlled by a Y-select signal reduces read-port current consumption.

A magnetic tunnel junction is formed by forming a first iridium lay, a first tungsten layer, a first ferromagnetic metal layer, a tunneling barrier layer, a second ferromagnetic metal layer, a secondtungsten layer, and a second iridium layer. The two ferromagnetic metal layers are a reference layer and a free layer respectively. The magnetization direction of the reference layer is fixed and cannot be reversed; The magnetization direction of the free layer can be reversed. When the magnetization direction of the reference layer is parallel to that of the free layer, the magnetoresistive device exhibits a low resistance state and stores '0' in the binary system; When the magnetization direction of the reference layer is antiparallel to that of the free layer, the magnetoresistive device exhibits a high resistance state, storing a '1' in binary. The invention can generate high tunneling magnetoresistive rate, improve read reliability of magnetic tunnel junction, and reduce device writepower consumption at the same time.

The invention discloses an asymmetric annular micro-electrode phase-change memory unit and a device, comprising a lower electrode layer, a first insulating layer, a phase-change functional layer, a second insulating layer, and an upper electrode layer from bottom to top; the first insulating layer There is a small hole in the layer, and the metal annular side wall and the insulating core are in the small hole; the phase change function layer is in contact with the lower electrode through the metal annular side wall in the small hole of the first insulating layer; the second insulating layer is also opened with a small hole; the upper electrode is in contact with the phase change functional layer through the small hole in the second insulating layer. Its core structure is characterized in that the lower electrode is a ring-shaped electrode, and the electrode core is filled with insulating material; the centerline of the first insulating layer, the centerline of the phase change functional layer, and the centerline of the second insulating layer are not on the same straight line. The asymmetric annular microelectrode phase-change memory unit and device provided by the present invention greatly reduce the contact area between the lower electrode and the phase-change material, reduce the operating current, have good thermal performance, and can maintain the original performance of the device. At the same time reduce power consumption and reduce thermal crosstalk.

The invention discloses a memorizer having a magnetoelectric random storage unit, comprising a plurality of magnetoelectric random storage units; a plurality of access transistors connected to first electrodes in the magnetoelectric random storage units; a plurality of word lines for controlling the access transistors; a plurality of first printed lines connected to second electrodes in the magnetoelectric random storage units; a plurality of first bit lines connected to the access transistors; a plurality of second bit lines connected to ferroelectric fixed layers in the magnetoelectric random storage units; and a plurality of second printed lines connected to ferromagnetic free layers in the magnetoelectric random storage units. The embodiment of the invention can write in information data with the electric field, and has the advantages of nonvolatility, low write-in power consumption, high storage density and the like.

The invention discloses a writing acceleration method for a phase change memory. The method comprises the steps of Partial-SET writing operation judgment and writing request execution, wherein in the step of Partial-SET writing operation judgment, the adopted writing pulse type of a current writing request in the phase change memory is determined as SET or Partial-SET pulse; in the step of writing request execution, quick Partial-SET writing acceleration of the phase change memory is realized by using a SET or Partial-SET method at different writing speeds of SET operation and RESET operation according to the writing pulse type. The invention also discloses a writing acceleration system for the phase change memory.

The invention provides a magnetic random access memory and a preparation method thereof, comprising: a magnetic tunnel junction structure; a word line, which is connected to the top of the magnetic tunnel junction structure; a read bit line, which is in contact with the bottom of the magnetic tunnel junction structure; The write bit line is located on one side of the read bit line; the U-shaped variable magnet connection structure includes a bottom edge, a side wall and an extension; the bottom edge is located below the read bit line, and one end is opposite to the write bit line connected, and the other end straddles the read bit line along the first direction; the sidewall portions are respectively located on opposite sides of the magnetic tunnel junction structure, and the top of the sidewall portion on the side of the magnetic tunnel junction structure away from the extension portion is connected to the word line The bottom of the sidewall portion is connected with the bottom edge portion; one end of the extension portion is connected with the sidewall portion, and the other end extends from the sidewall portion along the first direction to the direction away from the magnetic tunnel junction structure. The magnetic random access memory of the present invention reduces the current required for inversion of the magnetic tunnel junction structure, thereby reducing the required writing current and writing power consumption.

The invention provides a voltage-adjustable reluctance-variable random memory cell which comprises a bottom electrode layer, a ferroelectric oxide layer formed on the bottom electrode layer and a magnetic layer formed on the ferroelectric oxide layer, wherein the magnetic layer and the bottom electrode layer are respectively used as the upper and lower electrodes of the ferroelectric oxide layer to apply voltage on the ferroelectric oxide layer, the voltage direction is perpendicular to the ferroelectric oxide layer, and the ferroelectric oxide layer can adjust and control the arrangement of magnetic moment in the magnetic layer under the action of the voltage, so that the resistance of the magnetic layer in the set measuring direction changes. The invention also provides a memory with the reluctance-variable random memory cell. According to the invention, information data can be written by the voltage, and the voltage-adjustable reluctance-variable random memory cell has the advantages of nonvolatility, low writing power consumption, high storage density and the like.

The present invention is a magnetic tunnel junction with strong perpendicular magnetic anisotropy, its structure is ferromagnetic layer 1, potential barrier layer, and ferromagnetic layer 2 from bottom to top; it is characterized in that: the cross-sectional size of the magnetic tunnel junction is in Between 1nm and 150nm, the thickness of ferromagnetic layer 1 and ferromagnetic layer 2 is greater than 6nm, and the thickness of ferromagnetic layer 1 and ferromagnetic layer 2 is greater than half of the cross-sectional size; the thickness of the barrier layer is 0.2‑10nm . Compared with the existing technology, the device has the advantages of strong perpendicular magnetic anisotropy, high thermal stability, small cross-sectional size, high spin-transfer torque reversal efficiency, and fewer film layers.