37results about How to "Reduce write power consumption" patented technology

The invention relates to a spin Hall effect-assisted writing multi-state magnetic random access memory bit and a spin Hall effect-assisted writing method. The memory bit comprises a multi-state memory unit composed of two magnetic tunnel junctions, a spin Hall effect metal layer connected to a free layer of one of the magnetic tunnel junctions and a switch circuit composed of a word line, a bit line and a switching device. The multi-state magnetic random access memory composed of the spin Hall effect auxiliary bits has the magnetic random access memory (MRAM) advantages of fast reading speed, unlimited number of erasures, low energy consumption and radiation resistance, realizes polymorphic signal writing through spin Hall effect assistance, records 3 or 4 bits of information in the memory unit, effectively improves data storage density and reduces a chip area. The spin Hall effect can effectively reduce the writing current threshold and reduce the writing power consumption.

The invention relates to a magnetic tunnel junction with high perpendicular magnetic anisotropy, which structurally and sequentially comprises a first ferromagnetic layer, a barrier layer and a secondferromagnetic layer from bottom to top. The magnetic tunnel junction is characterized in that a size of a cross section of the magnetic tunnel junction is between 1nm to 150nm; thicknesses of both the first ferromagnetic layer and the second ferromagnetic layer are greater than 6nm, and the thicknesses of both the first ferromagnetic layer and the second ferromagnetic layer are greater than halfthe size of the cross section; and a thickness of the barrier layer is 0.2 to 10nm. Compared with the prior art, the magnetic tunnel junction has the advantages of high perpendicular magnetic anisotropy, high heat stability, small size of the cross section, high spin transfer torque turnover efficiency, small layer number of thin films and the like.

The invention provides a magnetic random access memory unit and a data writing method thereof. The magnetic random access memory unit comprises a spin orbital moment layer and at least one magnetic tunnel junction arranged on the spin orbital moment layer. The data writing method comprises: inputting a selection voltage to a magnetic tunnel junction of to-be-written data in the at least one magnetic tunnel junction; inputting writing current into the spin orbit moment layer at a preset time interval to enable the resistance state of the magnetic tunnel junction to correspond to-be-written data, wherein the writing current is smaller than the critical overturning current of the magnetic tunnel junction and larger than the critical overturning current of the magnetic tunnel junction when theselection voltage is input; and stopping inputting the selection voltage and the writing current in sequence. According to the method, deterministic overturning of the magnetic tunnel junction magnetic moment can be ensured, and the storage density is improved.

The invention discloses an asymmetric annular microelectrode phase change storage unit and device. The asymmetric annular microelectrode phase change storage unit comprises a lower electrode layer, a first insulating layer, a phase change function layer, a second insulating layer, and an upper electrode layer from bottom to top, the first insulating layer is provided with a small hole, a metal annular sidewall and an insulating core are arranged in the small hole, the phase change function layer is contacted with a lower electrode through the metal annular sidewall in the small hole of the first insulating layer, the second insulating layer is also provided with a small hole, and an upper electrode is contacted with the phase change function layer through the small hole of the second insulating layer. The asymmetric annular microelectrode phase change storage unit is characterized in that the lower electrode is an annular electrode, an electrode core is filled with an insulating material, and the center line of the small hole of the first insulating layer, the center line of the phase change function layer, and the center line of the small hole of the second insulating layer are all not in the same straight line. According to the asymmetric annular microelectrode phase change storage unit and device, the contact area of the lower electrode and the phase change material is greatly reduced, the operation current is reduced, the thermal property is good, the original property of the device can be maintained, the power consumption is reduced, and the thermal crosstalk is reduced.

The invention discloses a writing acceleration method for a phase change memory. The method comprises the steps of Partial-SET writing operation judgment and writing request execution, wherein in the step of Partial-SET writing operation judgment, the adopted writing pulse type of a current writing request in the phase change memory is determined as SET or Partial-SET pulse; in the step of writing request execution, quick Partial-SET writing acceleration of the phase change memory is realized by using a SET or Partial-SET method at different writing speeds of SET operation and RESET operation according to the writing pulse type. The invention also discloses a writing acceleration system for the phase change memory.

A polymorphic non-volatile solid-state memory cell based on a vertical read/write operation includes a bottom electrode layer, a ferroelectric piezoelectric layer formed on the bottom electrode layer,an intermediate electrode layer thereon, a pn junction layer adjacent to the intermediate electrode layer, and a top electrode layer thereon. The ferroelectric piezoelectric layer is used as the information writing layer and the pn junction layer is used as the information storage layer. The ferroelectric piezoelectric layer has a plurality of stress states under the vertical electric field, andthe pn junction layer has a plurality of non-volatile resistance states on the ferroelectric piezoelectric layer, so that the information can be written and erased. A read current or voltage is applied to the pn junction layer in a vertical direction so that information of the memory layer is read vertically. Vertical writing and reading of information and polymorphic features are conducive to greatly improve the storage density; the invention realizes information writing and erasing by utilizing an electric field, which is also conducive to reducing information access power consumption.

The invention provides a voltage-adjustable reluctance-variable random memory cell which comprises a bottom electrode layer, a ferroelectric oxide layer formed on the bottom electrode layer and a magnetic layer formed on the ferroelectric oxide layer, wherein the magnetic layer and the bottom electrode layer are respectively used as the upper and lower electrodes of the ferroelectric oxide layer to apply voltage on the ferroelectric oxide layer, the voltage direction is perpendicular to the ferroelectric oxide layer, and the ferroelectric oxide layer can adjust and control the arrangement of magnetic moment in the magnetic layer under the action of the voltage, so that the resistance of the magnetic layer in the set measuring direction changes. The invention also provides a memory with the reluctance-variable random memory cell. According to the invention, information data can be written by the voltage, and the voltage-adjustable reluctance-variable random memory cell has the advantages of nonvolatility, low writing power consumption, high storage density and the like.

The invention discloses a write circuit structure for a self-transfer torque magnetic random access memory. The write circuit structure for the self-transfer torque magnetic random access memory comprises a magnetic tunnel junction, a source line, a bit line, a word line, a first switching tube, a second switching tube, a control unit and a bistable circuit unit, wherein a free layer of the magnetic tunnel junction is connected with a drain of the first switching tube; a reference layer of the magnetic tunnel junction is connected with a source of the second switching tube; the source of the first switching tube is connected with the source line; the drain of the second switching tube is connected with the bit line; a first end of the bistable circuit unit is connected with the free layer of the magnetic tunnel junction and the input of the control unit; a second end of the bistable circuit unit is connected with the reference layer of the magnetic tunnel junction; an input end of the control unit is connected with each of the word line, the source line and the bit line; a first end of the bistable circuit unit and an output end of the control unit are connected with the grid of the first switching tube and that of the second switching tube. According to the write circuit structure, repeated writing action can be avoided, and the purposes of reducing the writing power consumption of an MRAM and the dynamic power consumption of a chip are achieved.

The invention discloses a transient storage circuit suitable for CMOS integration and a using method thereof, which relate to the technical field of radio frequency identification (RFID). The transient storage circuit consists of an access control circuit, a transient storage unit and an output sensitive amplifier which are connected with one another in turn. A reset signal PODR and an input data signal D IN of a digital circuit of a tag chip are written into the transient storage unit by the access control circuit, and the temporary data output Vc of the transient storage unit is amplified by the output sensitive amplifier and then is output by a data wire D_OUT. The transient storage circuit can solve the problem of lowered identification efficiency caused by short time power down of the tag chip in application of passive radio-frequency identification, reduces the time cost for tag identification, improves the identification efficiency of a passive radio-frequency tag, and has the characteristics of economical efficiency, simplicity and convenience.

A read-write circuit of a magnetic random access memory (MRAM) is characterized in that each data unit comprises a switch transistor, a magnetic tunnel junction (MTJ), a word line connection, a source line connection and a bit line connection, and the read-write circuit comprises a plurality of data units, a plurality of reference units, a bit line driving circuit and a source line driving circuit, a write-in voltage offset adjusting circuit is used for sensing voltage during write-in operation, a data selection circuit switches output of the voltage, a sensitive amplifier is in charge of effectively amplifying signals in combination with sequential control, data is converted into digital signals through the SR latch. A write termination circuit is used for controlling whether the write operation is completed or not according to the data signal output by the SR latch. According to the invention, a reading function, a writing function and a writing state monitoring function are respectively realized under different direct-current working points by adopting the same set of circuit, so that the power consumption can be reduced, and the reliability can also be improved.

The invention discloses a low-power-consumption magnetic random access memory and a writing and reading method thereof, the memory is mainly composed of a spin orbit moment material layer, a free layer, a tunneling layer, a reference layer, a pinning layer, an electrode and the like, and an antiferromagnetic insulator layer is added between the spin orbit moment material layer and the free layer and used for conducting and amplifying spin current. The writing method comprises the following steps of: writing a parallel state and an anti-parallel state, wherein numbers 0 and 1 are respectively and correspondingly written; and the reading method comprises the following steps of: enabling a current to flow through the tunnel junction from the reading electrode, and then forming a closed loop by the other electrode, so that data reading operation is realized. According to the invention, the current conversion efficiency can be improved, and the critical flip current density is reduced, thereby reducing the write-in power consumption; and according to the method, a writing path and a reading path are completely separated, so that the thickness of a tunneling layer can be increased, and the TMR resistance is improved.

The invention relates to a full subtractor applying an MTJ, which solves the problem that the writing power consumption is increased due to a mode of adding an MOS tube in a power supply voltage direction when the MTJ of the full subtractor is written at any time in the prior art, and belongs to the technical field of electronic circuits. The invention discloses a full subtractor applying an MTJ. The full subtractor comprises a one-bit full subtractor, two write-in circuits and two clock logic control circuits, clock signals output by the two clock logic control circuits are simultaneously sent to the two write-in circuits; the clock logic control circuits are realized by NOR gate circuits; three inputs of the clock logic control circuit comprise a full subtractor work clock, a forward/reverse write-in enable control signal and a forward/reverse write-in input clock signal. The clock of the write-in circuit is controlled by adding the control gate, the number of MOS tubes in the clock power supply voltage direction of the write-in circuit is reduced, and the purpose of reducing write-in power consumption is achieved.

The invention discloses a write circuit structure of a spin-torque transfer magnetic random access memory. The write circuit structure comprises a magnetic tunnel junction, and a source line, a bit line and a word line, a first switch tube, a second switch tube, a control unit and a capacitor, wherein a free layer of the magnetic tunnel junction is connected with a drain electrode of the first switch tube, a reference layer of the magnetic tunnel junction is connected with a source electrode of the second switch tube; the source electrode of the first switch tube is connected with the source line, and the drain electrode of the second electrode is connected with the bit line; one end of the capacitor is grounded, and the other end is connected to the input end of the control unit and is connected with the drain electrode of the first switch tube or the free layer of the magnetic tunnel junction; the input end of the control unit is respectively connected with the wore line, the source line or the bit line, and the drain electrode of the first switch tube or the free layer of the magnetic tunnel junction; the output end of the control unit is connected with the grid electrodes of the first switch tube and the second switch tube. Through the adoption of the write circuit structure disclosed by the invention, the repeated write action can be avoided, the aim of lowering the MRAM write power consumption and the chip dynamic power consumption is achieved.