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Column address decoding circuit of memory

A column address decoding and memory technology, applied in the field of semiconductor integrated circuit design, can solve problems such as long set-up time, complicated decoding methods, and affecting "reading" performance, and achieve the effect of ensuring data readout speed and simplifying circuit structure

Inactive Publication Date: 2014-06-18
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The disadvantage of the above circuit is that the high-voltage tube M2 is used as both a selection tube and an isolation tube, and its high threshold voltage is too long when the external power supply Vpwr5 is low, and the decoding method is complicated, which will also affect the "reading "performance

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Embodiment Construction

[0018] The column address decoding circuit of memory according to the present invention, such as figure 2 Shown:

[0019] After the input and output of the two inverters Inv1 and Ivn2 are connected in series, the output terminal of the second inverter Ivn2 is connected to the gate of the second NMOS N2, the drain of the second NMOS N2 is connected to the source of the first NMOS transistor N1, and the first NMOS The drain of N1 is connected to the output voltage CL of the memory cell, the gate of the first NMOS N1 is the input terminal of the fourth control signal Yev; the input terminal of the first inverter Inv1 is connected to the first control signal Ypre.

[0020] The drain of the third NMOS M1 is connected to the source of the second NMOS N2, and the source of the third NMOS M1 is an output terminal.

[0021] The first NMOS transistor N1 and the second NMOS transistor N2 mentioned above are all low threshold voltage transistors, and the third NMOS transistor M1 is a hi...

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Abstract

The present invention discloses a column address decoding circuit of a memory, wherein the selecting tube and the isolating tube of the traditional column address selecting circuit are separated, a high threshold voltage MOS transistor is adopted as an isolation effect, two low threshold voltage MOS transistors are adopted as a selecting effect, and a high voltage produced by a charge pump circuit is applied on the gate level of the high voltage tube so as to reduce influence of the high threshold voltage of the high voltage tube on the setup time and the reading performance, such that the column selecting circuit is substantially simplified, and the setup time of the column selecting circuit is substantially shortened.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit design, in particular to a memory column address decoding circuit. Background technique [0002] The role of the column selection circuit in the NVM (Non-Volatile Memory: non-volatile memory) readout circuit is to act as a selection circuit during a "read" operation, and as an isolation circuit for a high-voltage operation ("wipe" or "write"). Traditional implementation methods such as figure 1 As shown, it consists of two-level converters LS1 and LS2 and five MOS transistors, including two high-voltage PMOS P1 and P2, two high-voltage NMOS N1 and M2, and a low-threshold voltage NMOS M1. The drain terminal of the NMOS M1 is connected to the storage unit CL, the source terminal is connected to the drain terminal of the high-voltage NMOS M2, and the source of the NMOS M2 is the output terminal BL of the column selection circuit. Use the high-voltage tube M2 as both a selection tube ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/26G11C16/06
Inventor 刘芳芳金建明
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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