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Memory device with delay tracking for improved timing margin

A technology of memory cells and memory arrays, applied in the field of electronics, can solve the problems of high power consumption, slow operation speed, etc.

Active Publication Date: 2014-06-25
QUALCOMM INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, designing for worst-case process variation may result in slower operating speeds and / or higher power consumption

Method used

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  • Memory device with delay tracking for improved timing margin
  • Memory device with delay tracking for improved timing margin
  • Memory device with delay tracking for improved timing margin

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Experimental program
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Embodiment Construction

[0021] Memory devices with delay tracking and good read and write timing margins are described herein. The memory device may be Random Access Memory (RAM), Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), Video RAM (VRAM), Synchronous Graphics RAM (SGRAM), Read Only Memory (ROM) ), flash memory, etc. The memory device may be a stand-alone device or may be embedded within another device such as a processor.

[0022] figure 1 A block diagram of a design of a memory device 100 with delay tracking is shown. The memory device 100 includes an address latch 110 , an address decoder and a word line driver 120 , a memory array 150 , a timing control unit 160 and an I / O circuit 170 .

[0023] The memory array 150 includes M rows and N columns of memory cells 152 , and further includes one row and one column of dummy cells 154 . In general, M and N can each be any value. A memory cell is a circuit that can store data values ​​and can be implemented in a variety of ci...

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PUM

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Abstract

The invention relates to a memory device with delay tracking for improved timing margin. The memory device that can provide good timing margins for read and write operations is described. In one design, the memory device includes a memory array, a timing control circuit, and an address decoder. The memory array includes memory cells for storing data and dummy cells to mimic the memory cells. The timing control circuit generates at least one control signal used for writing data to the memory cells and having timing determined based on the dummy cells. The timing control circuit may generate a pulse on an internal clock signal with a driver having configurable drive strength and a programmable delay unit. The pulse duration may be set to obtain the desired write timing margin. The address decoder activates word lines for rows of memory cells for a sufficiently long duration, basedon the internal clock signal, to ensure reliable writing of data to the memory cells.

Description

[0001] This case is a divisional application. The parent case of this case is that the international application number is PCT / US2008 / 065450, the application date is May 31, 2008, the application number after the PCT application entered the Chinese national phase is 200880017864.7, and the invention name is "with delayed tracking to obtain improved timing content Limited memory device" invention patent application. technical field [0002] The present invention relates generally to electronics, and more specifically, to memory devices. Background technique [0003] Memory devices are commonly used in many electronic devices such as computers, wireless communication devices, personal digital assistants (PDAs), and others. A memory device typically includes many rows and columns of memory cells. Each memory cell can store a data value, typically a binary "0" or "1." To read a given memory cell in a given row and a given column, the word line for that row is activated and th...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C7/22
CPCG11C11/419G11C7/22G11C7/227G11C8/00
Inventor 陈志勤郑昌镐
Owner QUALCOMM INC