Dual-Port SRAM Connection Structure

Abstract

The present disclosure provides a static random access memory (SRAM) cell. The SRAM cell includes first and second inverters cross-coupled for data storage, each inverter including at least one pull-up device and at least two pull-down devices; at least four pass gate devices configured with the two cross-coupled inverters; at least two ports coupled with the at least four pass-gate devices for reading and writing; a first contact feature contacting first two pull-down devices (PD-11 and PD-12) of the first inverter; and a second contact feature contacting second two pull-down devices (PD-21 and PD-22) of the second inerter. The invention further provides a dual-port SRAM connection structure.

Description

technical field [0001] The present invention relates generally to the field of semiconductor technology, and more particularly to SRAM cell structures. Background technique [0002] In deep submicron integrated circuit technology, embedded static random access memory (SRAM) devices have become popular storage units for high-speed communications, image processing, and system-on-chip (SOC) products. For example, dual-port (DP) SRAM devices allow parallel operations such as IR (read) 1W (write) or 2R (read) within one cycle, and thus, have higher bandwidth than single-port SRAM. In advanced technologies with reduced feature size and increased packing density, low loading and high speed of cell structures are important factors in embedded memory and SOC products. Various gate structures are realized to achieve high packing density and high speed. For example, a U-shaped gate structure is adopted in the SRAM structure. However, U-shaped gate structures include potential issues...

AI Technical Summary

Problems solved by technology

However, the U-shaped gate structure includes potential issues with pull-down (PD) device variations and integration issues with fin field effect transistor (FinFET) structures

Also, critical dimension uniformity (CDU) in the U-shaped gate structure causes bottleneck and leakage issues

Accordingly, the U-shaped gate structure affects SRAM cell stability and limits scaling (or shrinking) capabilities

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