A method for making small-scale graphics

Abstract

The invention provides a manufacturing method for a small-sized graph. The manufacturing method comprises the steps that at first, the thin-film deposition process and the etching process are adopted for forming a large-sized graph and a first small-sized graph, and secondly, on the basis of the first small-sized graph, the thin-film deposition process and the etching process are adopted again for forming a second small-sized graph. The process of forming the second small-sized graph comprises the steps that a silicon oxide layer is deposited on the surface of a wafer, the plasma etching process is adopted for etching and removing the portion, on the top and the bottom of the side silicon nitride wall, of the silicon oxide layer, a side silicon oxide wall is formed on the side wall of the side silicon nitride wall, and the wet etching process is adopted for removing the side silicon nitride wall, so that the second small-sized graph is formed. As the two-time self-alignment process is adopted, the graph with the size smaller than that of a traditional small-sized graph can be manufactured, the device integration level is increased, the process window is enlarged, and the process difficulty is lowered.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for making small-scale graphics. Background technique [0002] With the continuous shrinking of the process size, especially 20nm and below, due to the further reduction of the gate width, the requirements for the capability of the lithography machine and the lithography process are getting higher and higher. According to Moore's law, in order to further reduce the critical size of the device and improve its integration, various methods for making small-scale graphics have emerged in the industry. [0003] Normally, see figure 1 , figure 1 It is a schematic flow chart of a traditional method for making small-sized graphics, which includes the following steps: [0004] Step L01: sequentially depositing a hard dielectric layer, a polysilicon layer, a bottom anti-reflection layer and a photoresist on the surface of the wafer; [0005] Step L02: Etching the photor...

AI Technical Summary

Problems solved by technology

[0010] However, in the actual etching process, there are problems of insufficient lithography capability and small process window in the technology of 20nm and below. Therefore, it is urgent to study a method to improve the lithography process window and reduce the critical dimension, so as to greatly improve Device integration

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