Inserting plug forming method

Abstract

The invention provides an inserting plug forming method. The inserting plug forming method includes performing first-time etching on a device area and a first dielectric layer to form a first connecting hole, filling the first connecting hole to form a first inserting plug, and forming a barrier layer and a second dielectric layer; performing second-time etching on the second dielectric layer to form a second connecting hole; performing third-time etching on the second dielectric layer and the barrier layer to form a third connecting hole, and filling the third connecting hole to form a third inserting plug. Due to step-by-step etching, depth-width ratio of the connecting hole formed by each etching process can be lowered, so that requirements on the etching processes are lowered, the etching processes are controlled better, and the inserting plugs good in shape are formed.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a plug. Background technique [0002] VLSL (Very Large Scale Integrated Circuit, VLSL) usually requires more than one layer of metal interconnection layer to provide sufficient interconnection capacity. Plug implementations in connection holes (contact holes). However, with the rapid development of semiconductor manufacturing technology today, semiconductor devices already have a deep submicron structure. With the gradual reduction of the critical size of the device, the size of the device region is also getting smaller and smaller, which leads to the smaller size of the plug. , which puts forward higher requirements on the connection hole etching process. [0003] Such as figure 1 As shown, in the prior art, several device regions 10 are formed on a semiconductor substrate (not shown), and shallow trench isolation layers (not shown) are formed b...

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Problems solved by technology

[0004] However, a part of the second plug 32 will be formed on the semiconductor substrate outside the device region 10, and when the connection hole is formed by etching, the etching will cause certain damage to the semiconductor substrate.

Moreover, since the size of the connection hole is getting smaller and the aspect ratio is getting larger and larger, the profile of the connection hole formed by the conventional one-step etching process is not ideal, resulting in the formation of the first plug 31 and the first plug 31. The shape of the second plug 32 does not meet the requirements, seriously affecting its electrical conductivity

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