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SiCoNi etching method for through-silicon-via morphology correction

A technology of through-silicon vias and topography, applied in electrical components, semiconductor/solid-state device manufacturing, circuits, etc., can solve problems such as low etching rate and achieve the effect of flattening

Active Publication Date: 2014-08-06
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] However, because SiCoNi etching technology has a very low etching rate for silicon, it cannot be directly used for etching the sidewalls of TSV vias.

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  • SiCoNi etching method for through-silicon-via morphology correction
  • SiCoNi etching method for through-silicon-via morphology correction
  • SiCoNi etching method for through-silicon-via morphology correction

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Embodiment Construction

[0024] In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be described in detail below with reference to specific embodiments and accompanying drawings.

[0025] The present invention provides a SiCoNi etching method for correcting the morphology of through-silicon holes. An oxygen plasma treatment step is added to the SiCoNi etching process to form a cycle of silicon oxide etching-through-hole sidewall oxidation-silicon oxide etching, and repeated The silicon atoms on the surface of the scalloped structure on the sidewalls of the through holes are consumed to obtain smoother sidewalls of the through-silicon holes. This will facilitate the conformal coverage of the subsequent silicon oxide insulating layer, copper barrier layer, and copper seed layer, and ultimately improve the interconnection characteristics and product reliability of TSVs.

[0026] figure 2 A flow chart of a SiCoNi etching metho...

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Abstract

The invention provides a SiCoNi etching method for through-silicon-via morphology correction. After a through hole with a silicon dioxide insulating layer formed on the side wall is formed in a semiconductor substrate of a wafer in a Bosch etching mode, the following steps are sequentially executed: (1) an etching agent is generated in a reaction cavity, wherein the semiconductor substrate is arranged on the initial etching position in the reaction cavity; (2) etching is conducted on the silicon dioxide insulating layer formed at the side wall of the through hole by using the generated etching agent in the reaction cavity; (3) the wafer is made to enter the heating position in the reaction cavity; (4) the wafer is heated at the temperature above 100 DEG C so as to conduct annealing treatment on the wafer; (5) gas in the reaction cavity is removed after annealing processing is conducted; (6) plasma treatment is conducted on the wafer by using oxygen; (7) the wafer returns to the initial etching position in the reaction cavity.

Description

technical field [0001] The present invention relates to the field of semiconductor manufacturing, and more particularly, to a SiCoNi etching method for correcting the morphology of through-silicon holes. Background technique [0002] With the improvement of the integration level of integrated circuits, the use of modern electronic packaging technology to achieve high-density integration (including 2.5D, 3D integration technology) has become an important technical approach to system-level integration of integrated circuits. Among many packaging technologies, Through-Silicon-Via (TSV) technology has become a hot spot of current research. TSV technology has many advantages, such as: the interconnect length can be shortened to be equal to the thickness of the chip, and the vertically stacked logic modules are used to replace Horizontally distributed logic modules; significantly reduce RC delay and inductance effects, etc. The TSV technology includes the following key processes:...

Claims

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Application Information

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IPC IPC(8): H01L21/768H01L21/02
CPCH01L21/76898
Inventor 雷通桑宁波
Owner SHANGHAI HUALI MICROELECTRONICS CORP