Transistor and formation method thereof

Abstract

The invention provides a transistor and a formation method thereof. The formation method of the transistor comprises: providing a semiconductor substrate, wherein the surface of the semiconductor substrate is provided with a plurality of separating layers, openings are formed between neighboring separating layers, the bottoms of the openings are provided with threshold voltage adjusting layers, and the threshold voltage adjusting layers are internally provided with doped ions; forming barrier layers on the surfaces of the threshold voltage adjusting layers and channel layers on the surfaces of the barrier layers, wherein the channel layers are at intrinsic states, and the barrier layers are used for preventing penetration by the doped ions in the threshold voltage adjusting layers; forming grid structures on the surfaces of the channel layers, wherein the surfaces of the grid structures are flush with the surfaces of the separating layers; removing the separating layers until the semiconductor substrate is exposed; and after the separating layers are removed, forming a doping layer on the surface of the semiconductor substrate at the two sides of the threshold voltage adjusting layers, the separating layers, the channels layers and the grid structures, wherein the surface of the doping layer is not lower than the surfaces of the channel layers. The formed transistor is lower in power consumption and stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a transistor and a forming method thereof. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the size of semiconductor devices in integrated circuits, especially MOS (Metal Oxide Semiconductor, metal-oxide-semiconductor) devices, has been continuously reduced to meet the miniaturization and development of integrated circuits. Integration requirements. In the process of continuous shrinking of the size of MOS transistor devices, the process of using silicon oxide or silicon oxynitride as the gate dielectric layer in the existing process is challenged. Transistors formed with silicon oxide or silicon oxynitride as the gate dielectric layer have some problems, including increased leakage current and diffusion of impurities, which affect the threshold voltage of the transistor and further affect the performan...

AI Technical Summary

Problems solved by technology

[0004] However, as the feature size of transistors continues to shrink, the threshold voltage VT of transistors cannot be reduced accordingly, resulting in excessive power consumption of transistors, which is not conducive to system integration

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