Hard mask laminated structure and fabrication method thereof

A technology of a stacked structure and a manufacturing method, which is applied in the manufacturing of semiconductor/solid-state devices, electrical components, circuits, etc., can solve problems such as unfavorable deposition and overhang structure, and achieve the effect of improving quality, simple process and avoiding holes.
CN104112698AActive Publication Date: 2014-10-22SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Authority / Receiving Office
CN · China
Current Assignee / Owner
SEMICON MFG INT (SHANGHAI) CORP
Publication Date
2014-10-22

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Abstract

The invention provides a hard mask laminated structure and a fabrication method thereof. The hard mask laminated structure comprises: a low-kappa medium hard film layer which is bonded onto the surface of a substrate; a fluorine and silicone glass layer which is bonded onto the surface of the low-kappa medium hard film layer; a metal hard film layer which is bonded onto the surface of the fluorine and silicone glass layer; and a shielding oxide layer which is bonded onto the surface of the metal hard film layer. According to the invention, the traditional tetraethoxysilane hard film layer HMTEOS is replaced with the fluorine and silicone glass layer, so the defect that the etching rate of the tetraethoxysilane hard film layer is slow compared with the low-kappa dielectric layer so as to form a overhanging structure can be overcome, and the generation of holes in the subsequent deposition process can be avoided, so that the deposition quality can be greatly improved, and the device stability and performance can be improved. According to the invention, the process is simple, so the structure and the method is suitable for being used in industry production.
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Description

technical field

[0001] The invention relates to a semiconductor structure and a manufacturing method thereof, in particular to a hard mask stack structure and a manufacturing method thereof. Background technique

[0002] As the integration of semiconductor devices continues to increase and the associated critical dimensions continue to decrease, the size of the vias in the interconnection (contact) and metal layer (metal) in the copper back-end interconnection process is also getting smaller and smaller. However, the aspect ratio remains the same or becomes larger, which makes the subsequent interconnection process more and more difficult. Especially in the process of 65nm and below, with the reduction of the thickness of the photoresist, the process difficulty of etching the via hole with only the photoresist as the barrier layer is getting higher and higher.

[0003] Therefore, a hard mask layer (Metal hard mask) is introduced to increase the selectivity ratio between the...

Claims

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