Method for manufacturing PMOS transistor

Abstract

The invention provides a method for manufacturing a PMOS transistor. The method includes the steps that grids are formed on a substrate, single-layer sacrifice side walls are formed around the grids, and the portions, at the bottoms of the sacrifice side walls, of the substrate are oxidized, so that oxides are formed; the sacrifice side walls serve as masks, the portions, on the two sides of each sacrifice side wall, of the substrate are etched, first grooves are formed, and the surfaces of the first grooves are exposed in air, so that oxides are formed; the oxides on the surfaces of the first grooves are removed through wet etching, the first grooves are etched so that second grooves can be formed, and part of openings of the second grooves are arranged at the bottoms of the sacrifice side walls; part of the sacrifice side walls are removed by certain thickness to the boundaries of the openings of the second grooves, and then the openings of the second grooves are completely exposed; first semiconductor materials are formed in the second grooves; second semiconductor materials are formed on the portions, between the remaining sacrifice side walls, of the substrate; the remaining sacrifice side walls are removed, side walls are formed around the grids, the side walls serve as masks, ion injection is conducted on the first semiconductor materials and the second semiconductor materials, and then source electrodes and drain electrodes are formed. By the adoption of the method, the performance of the formed PMOS transistor can be improved.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, in particular to a method for manufacturing a PMOS transistor. Background technique [0002] In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors. For PMOS transistors, embedded silicon germanium technology (Embedded SiGe Technology) can be used to generate compressive stress in the channel region of the transistor, thereby improving carrier mobility. The so-called embedded silicon germanium technology refers to embedding silicon germanium ...

AI Technical Summary

Problems solved by technology

[0009] The technical problem to be solved by the present invention is that the performance of the PMOS transistor formed by the prior art is not good

Images