Network-on-chip router with low buffer area and routing method

Abstract

The invention discloses a network-on-chip router with a low buffer area. The network-on-chip router comprises n input ports, n input registers, a routing computation module, a priority computation module, a port distribution module, a crossbar switch, p single microchip buffers and p output ports, wherein when microchips with high priority and secondary high priority compete for an effective output port, the port distribution module transmits the microchip with secondary high priority to the corresponding single micro-chip buffer according to a priority arbitration strategy, when other micro-chips with low priority compete for the port, a deflected output port is distributed; when the output port is idle, the microchip with secondary high priority is directly output to a lower routing node. According to the network-on-chip router, the area and the power consumption of a network-on-chip can be effectively reduced, meanwhile, the delay performance and the throughput performance are guaranteed, and the network-on-chip router with the low buffer area and the routing method are suitable for constructing a high-performance system on a chip.

Description

Technical field: [0001] The invention relates to the field of on-chip network design, in particular to an on-chip router design method and a routing method for reducing the buffer area. Background technique: [0002] In the field of integrated design of multi-core processors and IP cores, bus interconnection has become a bottleneck restricting the development of large-scale SoCs. The researchers used the design ideas of macroscopic computer parallel networks to propose a Network on Chip (NoC) interconnection method based on routing and packet switching technology, which effectively solved the global clock of bus interconnection, the delay of long interconnection lines, and the expansion issues such as limited resources. The network on chip is mainly composed of resource nodes (various IP cores), network interfaces, routing nodes, and interconnection channels. As the most critical part of the network on chip, the performance of the router on chip directly affects the overal...

AI Technical Summary

Problems solved by technology

However, the unbuffered router based on packet loss needs an additional response mechanism, and repeated packet sending leads to inefficiency; the adaptive routing feature of the deflection-based unbuffered router makes the routing path of the packet unpredictable, and there are data packets when the network traffic is large. The number of deflection increases and the delay increases. In addition, key data packets will also be transmitted on an uncertain path, which cannot provide quality of service guarantees

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