Semiconductor device and manufacturing method thereof
A manufacturing method and semiconductor technology, applied in the direction of semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as reducing reliability and damage, and achieve the effect of improving withstand voltage and reliability
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no. 1 approach
[0047] (Semiconductor device)
[0048] will be based on Figure 3 to Figure 4 A HEMT as the semiconductor device in the first embodiment is described. Notice image 3 is a top view of the semiconductor device according to the present embodiment, and Figure 4 for along image 3 A cross-sectional view of the semiconductor device taken by the dotted line 3A-3B. Although the description in this embodiment assumes that a plurality of HEMTs are formed on the same substrate, only one HEMT may also be formed.
[0049] The semiconductor device in this embodiment has layers formed on a substrate 11 including an initial growth layer 12, a buffer layer 13, an electron transit layer 21, an electron supply layer 22 and Cover layer 23. In addition, gate trench 50 is formed by removing part of capping layer 23 and electron supply layer 22 by dry etching in a region where gate electrode 41 is to be formed. The gate electrode 41 is formed on the inner sidewall and bottom of the gate tre...
no. 2 approach
[0083] (Semiconductor device)
[0084] Next, based on Figure 14 to Figure 15 A transistor having a UMOS structure as a semiconductor device in the second embodiment is described. Notice Figure 14 is a top view of the semiconductor device according to the present embodiment, and Figure 15 for along Figure 14 A cross-sectional view of the semiconductor device taken by the dotted line 14A-14B. Although the description in this embodiment assumes that a plurality of transistors having a UMOS structure are formed over the same substrate in this embodiment, only one transistor having a UMOS structure may also be formed.
[0085] The semiconductor device in the present embodiment has layers formed on the surface of a substrate 111 including a first semiconductor layer 121 , a second semiconductor layer 122 , and a third semiconductor layer 123 stacked in this order. Note that substrate 111 is an n-type substrate, for example, an n-GaN substrate. The first semiconductor layer...
PUM
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