mvb bus decoding and on-board recording system based on sopc technology
A recording system and bus technology, applied in the direction of registration/instruction, time register, registration/instruction of vehicle operation, etc., can solve the problems of complicated use, unsuitable for MVB bus analyzer, high cost, etc., and achieve convenient operation and real-time Good performance and high reliability
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[0038] figure 1It is the system block diagram of the MVB data decoding and on-vehicle recording system based on SOPC technology. include:
[0039] NIOS-II soft core, running SD card transfer protocol and FAT32 file system protocol program, designed to support SD card reading and writing under FAT32 file system;
[0040] The EPCS serial FLASH chip is used as the program memory, and the EPCS controller for bootloader download and loading;
[0041] The SDRAM chip is used as the memory of the processor, and the SDRAM controller that controls memory reading and writing;
[0042] The phase-locked loop frequency multiplier (PLL) provides a high-speed system operating clock for the NIOS-II soft core; at the same time, it provides an operating clock that is several times the MVB baud rate for the MVB decoding and data storage modules. The decoding operating clock should theoretically be Greater than twice the MVB baud rate, and the higher the multiple, the stronger the resolution an...
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