126 results about "Soft core processor" patented technology

The invention belongs to the field of image acquiring and processing, and particularly relates to an image acquiring and processing method based on an FPGA (field programmable gate array) serving as a control core. The method mainly includes building an image acquiring and processing SOPC (system on programmable chip) system comprising a Nios II soft-core processor module, a CMOS (complementary metal-oxide-semiconductor transistor) image sensing controller module, an FIFO (first in first out) controller module, an SDRAM (synchronous dynamic random access memory) controller module, a Canny edge detection algorithm module and a VGA (video graphic array) controller module. Firstly, images are acquired and then cached in the FIFO controller module; secondly, image data in the FIFO controller module are transmitted to an off-chip SDRAM chip by FPGA software and are stored in the off-chip SDRAM chip; thirdly, images in a memory are processed by means of an image processing algorithm, 'ping pong operation' is realized during processing, and the processing images are stored in the SDRAM again; and finally, the acquired edge images are displayed through a VGA interface after being processed.

The invention discloses a feedforward neural network hardware realization method based on multicore technology, relating to a computer system based on a specific calculation model. The invention adopts an NIOS II soft core processor and utilizes Quartus II software in an FPGA development system thereof to build a multicore processor system, the number of processor cores is only limited by chip scale, each processor core can be independently programmed, and multiple processor cores can simultaneously run respective program and simulate the characteristics of nerve cells of any kind by performing programming of one single core; in the network studying process, the single cores calculate output amount in a parallel mode and finish the adjustment of corresponding weights and thresholds; the input and output of each single core are performed with data exchange via a multiport memory to stimulate feedforward neural network with any structure, which realizes the purposes of high speed, distribution and parallel calculation of the neural network.

The invention relates to an implementing method of a numerical control system programmable logic controller (PLC) on the basis of a system on a programmable chip, which comprises the following steps of: constructing an external circuit connected with an FPGA (Field Programmable Gate Array); constructing the system on the programmable chip on the FPGA, wherein the system on the programmable chip is used for operating the numerical control system PLC; clipping, transplanting and compiling a real-time operation system in the system on the programmable chip; and operating the PLC on the real-time operation system to realize control on peripherals. In the invention, due to the adoption of the design of the system on the programmable chip on the basis of the FPGA, the integration level and the reliability of a programmable logic device are improved; and due to the adoption of a technology on the basis of the SOPC (System On Programmable Chip), a soft core processor is internally realized for executing a PLC task, the processing speed of the PLC is improved, and the cost is reduced when the flexibility is ensured.

The present invention relates to a USB interface control panel on-line update method, comprising steps of: the embedded soft-core processor, after receiving through USB module the on-line update command from the host computer, receiving update data sent from the host computer, and storing the update data into the volatile memory of the embedded soft-core processor; erasing the original embedded soft-core processor firmwares and/or FPGA configuration files stored in the non-volatile memory; writing the update data stored in the volatile memory into the non-volatile memory by means of programming. The present invention uses USB interface to realize the on-line updating of the control panel in the medical equipment and the like, wherein the control panel is capable of completely updating the embedded soft-core processor firmwares and/or FPGA hardware configuration files under the control of the host and without bringing interference to the normal operation by users.

The system transmits High Definition (HD) video/audio data, e.g. a JPEG2000-compressed video stream multi-channel audio stream, over a packet switching network, e.g. an Ethernet or IP network. Both the transmitter unit VTB and the receiver unit VRB feature a modular structure consisting of a base module or baseboard common to both units and one or more exchangeable adapter cards attached to or inserted into the baseboards to perform selected functions. The basebord is unitary, i.e. identical for both the VTB and the VRB; its components are activated depending upon the baseboard being in a VTB or a VRB. Each card is unique and earmarked and serves a specific purpose, e.g. for video coding and decoding, SMPTE processing, clocking/re-clocking, audio embedding/extraction. Upon inserting a card into a baseboard, the earmark is identified and the baseboard configured as transmitter or receiver baseboard. Functions in the baseboard can be implemented in Field Programmable Gate Arrays (FPGAs) and the network management, configuration, and/or control of the transmitting and/or receiving processes be performed by a softcore processors. This inventive combination of modular hardware/software results in a cost-effective, reliable, and fast system for transmitting large data volumes over packet switching networks.

The invention provides a binocular video splicing device based on an SOPC. The binocular video splicing device comprises an SOPC system making a NiosII soft-core processor as a core, wherein a pair of CMOS imaging sensors are connected with a pair of binocular video acquisition modules respectively through FPGA ports; the binocular video acquisition modules are connected with a binocular video storage module; one path of the output end of the binocular video storage module is connected with a binocular video output module through a feature extraction co-processor, and the other path of the output end of the binocular video storage module is connected with a binocular video display module; the binocular video output module is further respectively provided with the NiosII processor and an upper computer, and the binocular video display module is further connected with a VGA displayer. According to a binocular video splicing method, feature points are roughly matched through a Euclidean distance method, then partial mismatching points are extracted by means of a KNN method, a homograph matrix is calculated by the adoption of a RANSAC method at last, and real-time splicing for single-frame binocular video data is achieved through cylinder space conversion and linear weighing fusion.

The invention relates to the technical field of industrial Ethernet communication protocols, and discloses a POWERLINK communication protocol hardware realization method. In the embodiment of the invention, the method comprises steps: a data link layer and a physical layer interface of the POWERLINK communication protocol are realized based on any one chip selected from the following: a programmable logic device, a custom hardware chip and a semi-custom hardware chip; and the application layer of the POWERLINK communication protocol is realized based on any one mode selected from the following: a soft core processor, an embedded processor, and a general processor. POWERLINK master station equipment or slave station equipment obtained by adopting the realization method has a high data transmission response capability, high-speed and high-precision industrial field control requirements are met, the expansibility is more flexible, any object dictionary and any number of slave stations can be supported, the cost performance is good, and software and hardware are easy to realize and maintain.

The invention discloses a cable fault on-line detecting and positioning device. The device includes an FPGA module with an NIOS II soft core processor, a high-speed DA module, an isolation coupling module, a high-speed AD module and a conditioning circuit. The FPGA module provides clocks needed by all modules, generates a detection signal formed by modulation of an m sequence and sine waves, performs related operation processing of the detection signal and a reflection signal, and positions cable faults. The high-speed DA module is used for digital analog conversion of the detection signal generated by the FPGA module. The isolation coupling module isolates an output signal of the high-speed DA module and couples the output signal to a cable, and also isolates a reflection signal in the cable and couples the reflection signal to a detection positioning device. The high-speed AD module carries out analog-to-digital conversion of the reflection signal in the cable and then sends the signal to the FPGA module for processing. The conditioning circuit is used for conditioning the output signal of the high-speed DA module and an input signal of the high-speed AD module. The device has an on-line detection function, is high in positioning precision, and exhibits a high anti-interference capability.

The invention discloses a dual-network switching device based on a FPGA (field programmable gate array). The dual-network switching device comprises a FPGA chip, a first PHY (physical layer) chip, a second PHY chip, a first communication interface module and a second communication interface module, wherein the FPGA chip comprises a MicroBlaze soft core processor, an MAC (measurement and control) controller and an alternative controller; the MicroBlaze soft core processor is electrically connected with the MAC controller in a bidirectional manner; the MAC controller is electrically connected with the alternative controller in the bidirectional manner; the alternative controller is electrically connected with the first and the second PHY chips in the bidirectional manner respectively; the alternative controller is used for selectively connecting the MAC controller to one of the first and the second PHY chips; the first and the second PHY chips are respectively connected with the first and the second communication interface modules electrically in the bidirectional manner in a one-to-one correspondence manner. The invention further discloses a method for performing dual-network switching on the dual-network switching device based on FPGA. Dual-network switching is realized through hardware, so that communication instantaneity is improved.

The invention discloses an indoor intelligent video monitoring system based on SOPC, comprising a CCD camera, a holder, a stepping motor, a motor-drive circuit, a sensor group, a master controller combined by a Nios II soft core processor and a Cyclone II, a VGA display module, an alarm module and a computer terminal. The indoor intelligent video monitoring system is a platform for tracking an object and alarming by basing on a robot vision technology of the SOPC technology and the sensor technology, and is capable of alarming according to the setting values of temperature, humidity, smog and people activity and transmitting the alarm information to the remote user. The indoor intelligent video monitoring system based on the SOPC is a monitoring system which can finish the mission in the short time according to the user customization, can support the remote network monitoring, and is applicable to the household, the shopping mall and the library.

The invention discloses an FPGA (Field Programmable Gate Array) multi-mirror upgrading-loading method based on a soft-core processor. A single FPGA way is adopted, and the soft-core processor and control modules are embedded inside to implement an interface function; a program file caching function is implemented; and a chip scale interconnected bus interface function is implemented together with a CPLD (Complex Programmable Logic Device). The upgrading-loading method is implemented by an FPGA and the CPLD. The invention also discloses an FPGA multi-mirror upgrading-loading device based on the soft-core processor. The device comprises an upper computer, an interface receiving-transmitting module, an FPGA module, an external caching module, an external storage module and a CPLD module. Through adoption of the FPGA multi-mirror upgrading-loading method and device, FPGA multi-mirror rapid upgrading and flexible loading based on different application scenes are realized.

The invention relates to a PLC cooperative control device based on an SOPC technology. The device comprises two parts, a hardware system and a software system. The hardware system comprises an upper computer and a lower computer. The upper computer is formed by a Nios II soft core processor module, a memory module and a peripheral module, wherein the Nios II soft core processor module is composed of a CPU module, a TIMER0 module, a TIMER1 module, an UART module and a JTAG module. The software system comprises an embedded uC/OS-II real-time operating system, upper computer software, lower computer software and a virtual soft core PLC. The PLC cooperative control device is high in modifiability and transportability; the uC/OS-II real-time operating system is added, the operation real-time performance of the system is ensured, customized IP cores can be compiled according to specific requirements, and the required specific functions can be added freely; in addition, the number of I/O ports can be conveniently increased or reduced, so that the system is high in expansion and maintenance performance.

The invention relates to an MVB (Multifunction Vehicle Bus) bus decoding and on-vehicle recording system based on an SOPC technology. The system comprises an FPGA chip, an EPCS serial FLASH chip, an SDRAM chip, an SRAM chip, an SD card and an MVB level switching circuit, wherein the FPGA chip comprises an NIOS-II soft-core processor, a phase-locked loop frequency multiplier, an MVB decoder, an SRAM read/write controller, an SPI switching module and an SPI; the NIOS-II soft-core processor is connected with the EPCS serial FLASH chip, the SDRAM chip, the phase-locked loop frequency multiplier, the MVB decoder, the SRAM read/write controller and the SPI; the MVB decoder is connected with the phase-locked loop frequency multiplier, the MVB level switching circuit and the SRAM read/write controller; and the SPI switching module is connected with the SPI interface, the SRAM read/write controller and the SD card. Compared with the prior art, the MVB bus decoding and on-vehicle recording system disclosed by the invention has the advantages of software and hardware integration, high reliability, convenience in operation, high real-time property and the like.

The invention discloses a chip level PCR-LVCE integrated system which comprises a chip level PCR-LVCE micro fluidic chip, a chip level PCR-LVCE detection and a control interface circuit as well as a chip level PCR-LVCE detection and control system based on an SOPC (system on programmable chip) technique; the integrated system achieves ionophortic separation and electrochemical detection of different components of to-be-measured test samples in NIOSII soft core processor control, to-be-analyzed test sample micro mixing of relevant interface circuit control, micro fluid liquid direction judgment in an LVCE chip and variation field intensity forming movements on an LVCE separation micro channel. The chip level PCR-LVCE integrated system provided by the invention has the advantages of rapidity, simplicity, convenience, high integrated degree and the like, can effectively improve the detection efficiency, are higher in expansibility, real-time property and safety compared with the prior art, and can be widely applied to the fields of biochemistry, medicine, environment, criminal investigation and the like.

The invention discloses a hardware-in-the-loop generator which comprises a physical object part and a non-physical object part, wherein the non-physical object part is an upper computer loaded with waveform design simulation software; the physical object part is a lower computer; the lower computer comprises a D/A (Digital/Analogue) converter circuit, a signal conditioning circuit and an FPGA (Field Programmable Gate Array) chip in which an NiosII soft core processor is embedded; when the hardware-in-the-loop generator is in use, the non-physical object part can be used for calling an automatic mode by manual operation or program to set parameters of simulation waveform; if the displayed simulation waveform meets the requirement, module parameters are generated and transmitted to the lower computer and then are matched with an NiosII soft core processor and dual-port RAM (Random Access Memory) and DDS (Direct Digital Synthesizer) modules to transmit the processed digital signal to the D/A converter circuit; and finally, the processed digital signal is processed by the D/A converter circuit and the signal conditioning circuit to obtain a final signal. With the design, the hardware-in-the-loop generator disclosed by the invention has the advantages of higher precision, stronger intuitiveness, lower production cost, higher automatic degree and wide application range.

The invention provides a field programmable gate array (FPGA) logic module debugging and data acquisition method based on a PicoBlaze embedded soft core processor. The PicoBlaze embedded soft core processor, a universal asynchronous receiver/transmitter (Uart) module, a clock control module and a double-port random access memory (RAM) module are arranged in engineering of a hardware system, and corresponding software is installed on a personal computer (PC); a set of dedicated communication protocol is made, defines a uniform data packet format, is used for standardizing data exchange between the PicoBlaze processor and the PC, has a 8-bit cyclic redundancy check (CRC) function, and ensures communication reliability; and the hardware system on an FPGA is comprehensively debugged and all internal data is acquired and analyzed by sending a command at a PC end.

The invention discloses a system and a method for UDP high speed data transceiving. The system comprises an MAC layer, a UDP/IP protocol stack, a cache control module, a CI module and a soft core processor which are integrated in an FPGA, wherein the MAC layer is used for analyzing received data of an external physical layer, sending the data to the UDP/IP protocol stack, packing data from the UDP/IP protocol stack and sending the packed data to the external physical layer, the UDP/IP protocol stack is used for analyzing received effective data of the MAC layer, sending the data to an application layer through the soft core processor, packing data from the application layer and sending the packed data to the MAC layer, the cache control module is used for controlling reading and writing of the external cache, and the CI module is used for controlling data interaction between the soft core processor and the UDP/IP protocol stack and between the soft core processor and the cache control module. According to the system, hardware logic processing is employed respectively for the protocol stack and cache control, the soft core processor is only for parameter configuration, the soft core processor is prevented from excessively interfering data transmission and storage, system bandwidth is greatly improved, and high speed data transceiving can be realized.