11 results about "Soft core processor" patented technology

The invention discloses a satellite-borne laser communication telemetering and remote control system and a multi-protocol interface unified management method thereof, and relates to the technical field of aerospace measurement and control and embedded systems, the satellite-borne laser communication telemetering and remote control system comprises an on-chip system which takes an FPGA as a hardware platform and is constructed in cooperation with a MicroBlaze soft core processor and a Verilog program, and layered architecture is carried out; the upper-layer task management module is responsible for configuration, execution and data monitoring of task instructions and unified management and control of different load devices; the communication interface middleware module is used for abstracting and packaging a bus CAN (Controller Area Network), an interface RS422 and an underlying communication interface of the Ethernet; by introducing the interface middleware and realizing based on the MicroBlaze soft core processor, an upper-layer application and a bottom-layer hardware interface are separated, various communication interfaces are supported, the interface coupling degree is reduced, and unified scheduling and centralized management of the communication interfaces are realized, so that the telemetering and remote control system can efficiently run in a multi-task and multi-interface environment; and flexible configuration and expansion are supported.

The application discloses a programmable multi-mode precision time trigger system and method based on PTP, and relates to the field of time synchronization control.The system adopts a soft and hard cooperative architecture of a master control FPGA, and realizes nanosecond-level marking of a PTP protocol and local clock locking by combining an Ethernet PHY, a high-precision DAC and a voltage-controlled crystal oscillator in the FPGA internal hardware logic; a soft core processor is embedded to run Kalman filtering and PID algorithm to output a smooth correction amount.Based on the high-precision reference, a hardware trigger generates an IP core to support three trigger modes of immediate, absolute and relative, and can read a timing table from a memory to output a single pulse, an equal-interval pulse train and an unequal-interval pulse train waveform.Meanwhile, an event queue is built-in to support group management of more than one hundred events and quick cancellation of unexecuted events.The application overcomes the defects that the precision and flexibility of a traditional timing scheme are difficult to be considered, and meets the extremely high standard cooperative synchronization demand of a large scientific experiment and an industrial system with an accuracy of better than ± 50 ns.

The invention provides an aerospace SOPC system based on a Loongson LA132 soft core processor, and the system comprises an on-chip system hardware unit which takes the Loongson LA132 soft core processor as a core, carries out the RTL design through a hardware description language, and achieves the configuration, connection and integration of the processor, a memory and peripheral equipment; the Makefile software compiling unit is used for generating a program code suitable for the Loongson LA132 soft core processor and supporting customized software development and deployment; the fault-tolerant unit is used for storing a bit configuration file of the FPGA and a program code of the processor in NOR Flash through a triple redundancy storage technology, performing consistency comparison on the program code through one-out-of-three operation when the system is started, loading a correct program code to the instruction RAM module, and performing error check and correction by adopting RS (12, 8, 4) codes when the processor is accessed; and errors caused by single event upset are prevented.

The invention relates to an equipment data writing method and device, equipment, a storage medium and a program product, and relates to the technical field of equipment data processing. The method comprises the steps of receiving a data frame carrying to-be-written data in response to a user engine, and writing the to-be-written data into a target memory module based on the user engine; sending a data write command to the first target device based on the first soft core processor; the data writing command is used for the first target device to trigger a data writing function and send feedback information; one soft core processor corresponds to one target device, and the first soft core processor corresponds to the first target device; in response to the feedback information, sending a data acquisition request for the to-be-written data to a user engine; the user engine is used for acquiring the to-be-written data in the target memory module according to the data acquisition request and writing the to-be-written data corresponding to the data acquisition request into the first target device through the protocol controller core connected with the first target device. By adopting the method, the multi-device synchronous writing requirement can be met.

The invention belongs to the related technical field of computer hardware, and discloses an FPGA-based PCIe root complex integration system, which comprises a soft core processor, a memory module and an I / O module, when the soft core processor responds to a PCIe transmission task, an AXI transaction is sent to an XDMA module, the XDMA module packages the AXI transaction into a PCIe TLP packet, and the PCIe TLP packet is sent to endpoint equipment through a PCIe link; when the soft-core processor responds to the UART interrupt request, the soft-core processor sends the UART request to the UART module through a control interface of the soft-core processor, and the UART module starts a data transceiving interface of the soft-core processor to realize data interaction between the soft-core processor and external equipment; when the soft core processor responds to the PCIe link interruption request, the soft core processor sends the PCIe link request to the XDMA module, the XDMA module receives a PCIe TLP packet returned from the PCIe link, analyzes the PCIe TLP packet into an AXI transaction and then returns the AXI transaction to the soft core processor, and the soft core processor stores the received AXI transaction in the corresponding SDRAM. According to the PCIe root complex integrated system, the power consumption and the size of the PCIe root complex integrated system can be reduced, the transmission delay is reduced, and the interruption delay and the bus competition are reduced.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention discloses a soft and hard collaborative analog-to-digital converter calibration method based on adaptive moment estimation, which solves the problem that the traditional software calibration cannot meet the high sampling rate throughput through high-speed statistics of FPGA hardware logic processing mass data. An ADAM optimization algorithm is operated through an embedded soft core processor, the updating step length of each parameter is dynamically adjusted through second-order moment estimation, and the problems of LMS algorithm oscillation and local optimum caused by nonlinearity of an analog delay line are effectively solved; and in combination with a hierarchical calibration strategy, dual improvement of calibration speed and precision is realized.

A hardware security module including a field programmable gate array (FPGA) is presented. In use, the FPGA is configured to provide a soft core processor for executing program code. This enables the configuration of the soft core processor to be altered over the life cycle of the HSM based on instructions received by the FPGA. In addition, the FPGA is used such that different configurations can be provided when the HSM is used by different corresponding users (tenants). In addition, the use of the FPGA enables different instances of the HSM to have different configurations more cheaply.

A system and method for securing a system-on-chip (SoC) field programmable gate array (FPGA) is provided, wherein the SoC FPGA includes an FPGA fabric, a soft core processor hosted within the FPGA fabric, a hard core processor, and a secure boot environment for the SOC FPGA. Monitoring logic monitors for a change in the FPGA fabric. External watchdog logic is configured to receive a trigger signal from the monitoring logic, and force the hard core processor(s) of the SoC FPGA into a reset state with no ability to recover unless power is cycled when a change has been made to the FPGA fabric, so as to provide a “fail secure” scenario. The monitoring logic may be firmware hosted on the FPGA fabric, software hosted on the soft core, software hosted on the hard core, and / or external hard logic.

The invention relates to an implementation method of an embedded exFAT file system based on an FPGA and data recording equipment. The implementation method comprises the steps of FPGA hardware platform construction, FatFs file system transplantation and exFAT extension, operation instruction processing pipeline architecture, realization of processing core and peripheral control on a single FPGA chip, cost and complexity reduction, abundant high-speed interface resources and customized IP core development capability, so as to construct a high-performance storage subsystem. The invention further discloses an embedded type large-capacity data recording device based on the FPGA soft core processor MicroBlaze.

The invention relates to a system for realizing wireless signal storage and accumulation based on an FPGA (Field Programmable Gate Array), which comprises a radio frequency transceiving chip, the FPGA, an Ethernet PHY (Physical Layer) chip, a serial port chip, a serial port upper computer, a network port upper computer and a DDR (Double Data Rate) memory, and is characterized in that the radio frequency transceiving chip is connected with the FPGA, the radio frequency transceiving chip is used for transceiving wireless signals, the FPGA is connected with the serial port upper computer through the serial port chip, and the Ethernet PHY chip is connected with the DDR memory through the Ethernet PHY chip. The FPGA sends the data to a network port upper computer through the Ethernet PHY chip, and the DDR memory stores the data received by the radio frequency transceiver chip. By adopting the system and the method for realizing wireless signal storage and accumulation based on the FPGA, real-time coherent accumulation can be met by utilizing the high-speed read-write characteristic of a DDR (Double Data Rate) memory, the number of taps and the number of storage frames of each tap can be dynamically adjusted according to actual application requirements, the problem of low resource utilization rate caused by a fixed tap architecture is effectively solved, and the system and the method have high practicability. And the method is suitable for burst communication or complex electromagnetic environment. The Microblaze soft core processor receives a control instruction of an upper computer and adjusts tap parameters in real time, so that the real-time defect of a software adjustable scheme is avoided, and the real-time requirement of high-speed signal processing is met.