Forming method of conductive plug
A technology of conductive plugs and interlayer dielectric layers, which is applied in the manufacture of circuits, electrical components, semiconductors/solid-state devices, etc., and can solve the problems of high failure density of tungsten plugs and affecting the performance of semiconductor devices, etc.
Inactive Publication Date: 2015-02-11
SEMICON MFG INT (SHANGHAI) CORP
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Problems solved by technology
[0006] In the prior art, the failure density of tungsten plugs on the substrate is relatively high, which affects the performance of subsequent semiconductor devices
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[0034] After analysis, it is found that in the prior art, the failure density of the tungsten plugs on the substrate is relatively high. Wherein, there are three cases of failure of the tungsten plug on the substrate: failure of the source tungsten plug, failure of the drain tungsten plug, failure of both the source tungsten plug and the drain tungsten plug.
[0035] The following is an example of simultaneous failure of the source tungsten plug and the drain tungsten plug on the substrate. The failure density of the tungsten plug on the substrate is relatively high, and the reasons for affecting the performance of the subsequently formed semiconductor device are as follows:
[0036] refer to figure 1 , performing chemical mechanical polishing on the aluminum layer to the first interlayer dielectric layer 11 to form the aluminum gate 12 . After the aluminum layer is planarized to the first interlayer dielectric layer 11 by chemical mechanical polishing, a residue 13 is forme...
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Abstract
The invention relates to a forming method of a conductive plug. The forming method comprises the following steps of providing a substrate which is provided with a source and a drain, forming a first interlayer dielectric layer with an opening in the substrate, filling a metal layer in the opening, covering the surface of the first interlayer dielectric layer by the metal layer, and chemically and mechanically polishing the metal layer to the first interlayer dielectric layer so as to form a metal grid, wherein chemical and mechanical polishing residues are formed on the surface of the first interlayer dielectric layer; etching one thick part of the first interlayer dielectric layer to remove the residues; forming a second interlayer dielectric layer on the remained first interlayer dielectric layer and the surface of the metal grid; forming a source through hole and a drain through hole in the second interlayer dielectric layer and the first interlayer dielectric layer, wherein the source through hole is formed in a source, and the drain through hole is formed in a drain; filling the source through hole and the drain through hole with conductive layers to form a source conductive plug and a drain conductive plug. The method has the advantages that the failure density of the conductive plugs on the substrate is reduced, and the property of a subsequently formed semiconductor device is further improved.
Description
technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a conductive plug. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. This development makes the surface of the wafer unable to provide enough area to manufacture all the components. required interconnection wires. [0003] In order to meet the requirements of interconnection lines after shrinking components, the design of two or more layers of multilayer metal interconnection lines has become a method commonly used in VLSI technology. At present, the conduction between different metal layers or devices in the metal layer and the substrate is realized through conductive plugs in the dielectric layer between the metal layers or between the metal layers and the substrat...
Claims
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Login to View More IPC IPC(8): H01L21/768
CPCH01L21/76897
Inventor 黄敬勇张城龙张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP