Preparation method of nano-twinned copper rewiring

Abstract

The invention provides a method for preparing nano-twinned copper rewiring, comprising the steps of: 1) preparing a passivation layer on a substrate, and photoetching a window for interconnection with a chip plate; 2) forming a passivation layer on the surface of the passivation layer and A seed layer is formed in the interconnection window; 3) a photoresist pattern of nano-twinned copper rewiring is formed on the surface of the seed layer, and a layer of nano-twinned copper rewiring layer is prepared on the surface of the exposed seed layer by pulse electroplating; 4 ) to remove the photoresist pattern and etch away the excess seed layer. The invention adopts pulse electroplating supplemented by rapid annealing treatment, relies on the large internal stress formed by pulse electroplating to drive copper recrystallization, and forms high-density nano twins for rewiring. The current density adopted by the present invention is low, the current equipment can be used, and it is fully compatible with the existing IC technology, belongs to the wafer-level packaging technology, has high efficiency and low cost. The prepared nano-twinned copper has excellent comprehensive mechanical properties, can greatly reduce the rewiring size to about 10um, and has high thermomechanical reliability.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, in particular to a preparation method of nano-twinned copper rewiring. Background technique [0002] Wafer-level packaging means that chips and packages are manufactured and tested on the wafer, and finally diced. The first step of wafer-level packaging is to expand the pitch of standard IC pads through rewiring technology, and then perform low-cost ball planting to increase the pitch and size of solder balls, ensuring higher board-level reliability. [0003] Rewiring technology is the core process of wafer level packaging, which directly determines the excellent packaging performance. Compared with the chip size, the rewiring distance is often longer and has larger parasitic effects. Rewiring often requires a turn in the routing direction to coordinate other solder joints and wiring to achieve high-density packaging. Rewiring needs to be connected with solder balls through UBM, which be...

AI Technical Summary

Problems solved by technology

[0006] In view of the above, there is currently no publication of any technology for pulse-plated nano-twinned copper redistribution compatible with wafer-level processes

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