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Array substrate and preparation method thereof, display device

A technology for array substrates and display areas, applied in semiconductor/solid-state device manufacturing, electrical components, electric solid-state devices, etc., can solve the problems of low production efficiency and high production cost of oxide thin film transistors, reduce the number of patterning processes and improve production Efficiency and reduction of production time

Active Publication Date: 2015-03-04
BOE TECH GRP CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] In order to solve the above problems, the present invention provides an array substrate and its preparation method, and a display device, which are used to solve the problems of low production efficiency and high production cost of oxide thin film transistors in the prior art

Method used

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  • Array substrate and preparation method thereof, display device
  • Array substrate and preparation method thereof, display device
  • Array substrate and preparation method thereof, display device

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Embodiment 1

[0032] As an embodiment of the present invention, the array substrate provided in Embodiment 1 of the present invention is an array substrate structure in which the gate layer is located on the bottom layer, but the structure of the array substrate in Embodiment 1 of the present invention is also applicable to the array substrate structure in which the gate layer is located on the top layer .

[0033] image 3 It is a flow chart of a method for manufacturing a thin film transistor provided in Embodiment 1 of the present invention. Such as image 3 As shown, the preparation method of the thin film transistor comprises:

[0034] Step 3001, forming a gate in the display area, and forming a first gate metal in the connection area.

[0035] Figure 4 It is a schematic diagram of forming the first source-drain metal, gate and gate insulating layer in the first embodiment. Such as Figure 4 As shown, a gate metal film is formed on the substrate, and the thickness of the gate me...

Embodiment 2

[0054] As an embodiment of the present invention, the array substrate provided in Embodiment 1 of the present invention is an array substrate structure in which the gate layer is located on the bottom layer, but the structure of the array substrate in Embodiment 1 of the present invention is also applicable to the array substrate structure in which the gate layer is located on the top layer .

[0055] Figure 13 It is a schematic structural diagram of a thin film transistor provided in Embodiment 2 of the present invention. Such as Figure 13 As shown, the array substrate includes a base substrate, the base substrate includes a display area, and the display area is provided with a gate 101, a gate insulating layer 103, an active layer 104, a source 106, and a drain 107, The source electrode 106 and the drain electrode 107 are completely located above the active layer 104, thereby shortening the process time, improving the production efficiency and reducing the production cos...

Embodiment 3

[0060] Embodiment 3 provides a display device, including any array substrate provided in Embodiment 2. For specific content, refer to the description in Embodiment 2 above, which will not be repeated here. The display device may be any product or component with a display function such as a liquid crystal panel, an electronic paper, an OLED panel, a mobile phone, a tablet computer, a television set, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.

[0061] In the display device provided in the third embodiment, the active layer, the source electrode and the drain electrode are formed through a patterning process, and the source electrode and the drain electrode are arranged above the active layer so as not to affect the quality of the thin film transistor. The use frequency of the mask plate is reduced under the premise, and compared with the prior art, the number of patterning processes is further reduced, the production process is simplified, t...

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Abstract

The invention provides an array substrate and a preparation method thereof, and a display device. The preparation method of the array substrate includes: forming a grid and a grid insulating layer in a display area of a substrate; forming an active layer, a source and a drain by a one-time pattern composition process, wherein the source and the drain are arranged on the active layer. According to the array substrate and the preparation method thereof and the display device provided by the invention, the active layer, the source and the drain are formed by the one-time pattern composition process, and the source and the drain are arranged on the active layer to reduce the number of use of a mask plate under the premise of not influencing the quality of a thin-film transistor; compared with the prior art, the times of the pattern composition process is further reduced, the manufacture technology is simplified, the production efficiency is improved, the manufacture time is shortened, and the production cost is lowered.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a preparation method thereof, and a display device. Background technique [0002] Oxide thin-film transistor (Oxide TFT) has the advantages of ultra-thin, light weight, and low power consumption. It can not only be used in the manufacture of liquid crystal display panels, but also for the production of a new generation of organic light-emitting display panels with brighter colors and clearer images. OLED (Organic Light-Emitting Diode, Organic Light-Emitting Diode) is available in the practical stage. [0003] figure 1 It is a structural schematic diagram of a thin film transistor in the prior art, figure 2 for figure 1 Flowchart of the fabrication method of the shown thin film transistor. Such as figure 1 and figure 2 As shown, the preparation method includes: step 2001, forming a gate 101 and a common electrode line 102 on a base substrate, s...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L21/77
Inventor 袁广才
Owner BOE TECH GRP CO LTD
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