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All-side-pin-free flat semiconductor device packaging structure and method

A four-sided no-lead, device packaging technology, which is applied in semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve the problems of low production efficiency, extra heat of wires, limited current carrying capacity of semiconductor devices, and poor reliability and other issues, to achieve the effect of improving production efficiency, saving bridge frame placement machines, and low parasitic voltage

Active Publication Date: 2015-03-25
GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The present invention is completed in order to solve the above-mentioned deficiencies in the prior art. The purpose of the present invention is to propose a four-sided non-lead flat semiconductor device packaging structure and packaging method. When packaging, more wires generate extra heat, the current carrying capacity of semiconductor devices is limited, and the production efficiency is low and the reliability is poor.

Method used

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  • All-side-pin-free flat semiconductor device packaging structure and method
  • All-side-pin-free flat semiconductor device packaging structure and method
  • All-side-pin-free flat semiconductor device packaging structure and method

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Embodiment 1

[0053] figure 1 It is the overall structure diagram of the four-sided leadless flat semiconductor device package structure provided by the first embodiment of the present invention. Such as figure 1 As shown, the package structure includes:

[0054] Lead frame 100 and bridge frame 200.

[0055] figure 2 It is the lead frame structure diagram of the four-sided leadless flat semiconductor device package structure provided by the first embodiment of the present invention. Such as figure 2 As shown, the edge of the lead frame is provided with a plurality of cutting positioning marks 110. When the semiconductor device is packaged with this packaging structure, the bridge frame is stacked on the lead frame, and when stacked, the cutting positioning marks on the lead frame are exposed. At least one first positioning bayonet 120 is provided on the lead frame, which is mutually engaged with the second positioning bayonet on the bridge frame when used for packaging, so that the positionin...

Embodiment 2

[0078] Image 6 It is a flowchart of a four-sided leadless flat semiconductor device packaging method provided in the second embodiment of the present invention. Such as Image 6 As shown, the packaging method includes:

[0079] Step 601: Dicing the wafer to obtain multiple chips.

[0080] In this step, the wafer with multiple chips is cut to obtain multiple chips.

[0081] Step 602: Provide a lead frame. A plurality of cutting positioning marks are provided on the edge of the lead frame, and the cutting positioning marks divide the lead frame into multiple rows and multiple columns of connected lead frame units.

[0082] In this step, the lead frame structure and the lead frame unit structure are as described in the first embodiment.

[0083] Step 603: Prepare conductive bonding material on the first chip holder, the first chip gate pin and the second chip holder.

[0084] In this step, the conductive bonding material is coated on the first chip holder, the first chip gate pin and th...

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Abstract

The invention discloses an all-side-pin-free flat semiconductor device packaging structure and method. The packaging structure comprises a lead frame and a bridge frame. The edge of the lead frame is provided with a plurality of cutting positioning marks. The cutting positioning marks partition the lead frame to lead frame units connected in a multi-row and multi-column mode. The bridge frame comprises bridge frame units connected in a multi-row and multi-column mode. When packaging is conducted, the bridge frame is arranged on the lead frame in a stacked mode, the cutting positioning marks are exposed, and the bridge frame units cover the lead frame units. The all-side-pin-free flat semiconductor device packaging structure has the following advantages that the current bearing capacity of a semiconductor device is improved, and a copper bridge can absorb the heat generated by chips instantaneously; the package cost is reduced; lower stray voltage is provided; production efficiency and package reliability are improved, integrated package to the maximum degree is achieved, and the utilization space is greatly increased.

Description

Technical field [0001] The present invention relates to the field of semiconductor technology, in particular to a four-sided leadless flat semiconductor device packaging structure and packaging method. Background technique [0002] With the development of semiconductor technology, semiconductor devices are required to be smaller in size and higher in power. However, high current and high thermal resistance caused by small size and high power are the main problems that plague semiconductor devices. In order to solve this problem, the use of dual lead frames for packaging has become an increasing choice. In the prior art, when a semiconductor device is packaged with a dual lead frame, more wires are used for connection, and more wires will generate additional heat and increase the burden on the semiconductor device. In addition, the current carrying capacity of the wires is limited, which causes the semiconductor device to suffer The current carrying capacity is limited, and this ...

Claims

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Application Information

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IPC IPC(8): H01L23/495H01L21/56
CPCH01L2224/34
Inventor 袁家锦徐振杰曹周敖利波
Owner GREAT TEAM BACKEND FOUNDRY (DONGGUAN) LTD
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