An io bus device with self-identification function based on fpga
A bus device and self-identification technology, applied in the field of bus, can solve the problems of unreliable connection between boards and backplanes, inability to plug other types of boards, and wrong power boards, saving query or interruption time, The effect of convenient program processing and convenient replacement
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[0028] like figure 1 As shown, the present embodiment includes a main CPU board, slots for plug-in boards, three types of bus parallel bus, serial bus and field bus, and the main CPU board includes a CPU module and an FPGA module. These three buses are all connected to the slots. Each slot can use these three buses to send data. Except that the CAN bus is directly connected to the slot by the CPU, the rest are connected to the slot by the FPGA to manage the parallel bus and the RS485 bus in a unified manner.
[0029] Each slot has its own differences, and each slot has a CS chip select line connected to the FPGA, so that the FPGA can time-division multiplex the parallel bus.
[0030] The parallel bus is composed of CS chip select line, 2 RD_ID, 4 RD, 4 WR and 8 data lines, as shown in Table 1.
[0031] Table 1 Definition table of specific terminals of the bus
[0032] A B C 1 CS 2 3 DATA1 DGND DATA0 4 DATA3 DGND DATA2 ...
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