A Digital Phase Detector for GPS Taming Crystal Oscillator

A digital phase detector and crystal oscillator technology, applied in the field of digital phase detectors, can solve the problems of slow phase-locked loop adjustment speed, phase 2π ambiguity, and long capture time, so as to improve the ability of anti-edge jitter, improve the locking speed, The effect of improving the accuracy of phase discrimination

Inactive Publication Date: 2017-10-27
SOUTH CENTRAL UNIVERSITY FOR NATIONALITIES
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] (1) The existing phase detector cannot directly measure the frequency deviation, but reflects the frequency deviation through the phase change difference, and the existing phase difference only measures the rising edge or the lower edge of the pulse signal, so that the frequency deviation measurement will be affected by the edge Influenced by jitter, measurement error increases
[0005] (2) In order to achieve high-precision frequency output in GPS taming active crystal oscillator applications, the signal used for phase detection requires a long period (above the second level), resulting in a very low sampling frequency for phase detection
High precision OCXO with high Q (up to 10 7 ), resulting in a very narrow voltage-controlled adjustable frequency range
The above two factors will lead to a slower adjustment speed of the PLL
Moreover, due to the randomness of the initial phase, when the existing double D flip-flop phase detector initially works, there are problems of phase lead and lag ambiguity. The lock state has entered the locked state (the capture process exceeds ten minutes or more)
Moreover, the narrower the frequency adjustment range of the OCXO, the higher the control accuracy requirements and the longer the capture time.
[0006] (3) During the process of OCXO tracking the reference frequency signal output by the GPS module, due to factors such as space weather changes and environmental interference, the GPS module will lose satellites. At this time, the reference frequency signal from the GPS module will appear larger disturbance and error
The digital phase detector that relies solely on measuring the phase deviation to reflect the frequency deviation has the problem of 2π ambiguity in the phase, so that when the phase deviation is too large, it will lead to errors in the calculation of the frequency deviation

Method used

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  • A Digital Phase Detector for GPS Taming Crystal Oscillator
  • A Digital Phase Detector for GPS Taming Crystal Oscillator
  • A Digital Phase Detector for GPS Taming Crystal Oscillator

Examples

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Embodiment 1

[0042] figure 1 It is the circuit structure and connection diagram of this patent. There are 3 input terminals, the first signal is the PPS signal from the GPS module, the second signal is the high-frequency clock signal from the OCXO, and the third signal is from the phase-locked loop. Outputs the coarse frequency lock status signal. There are 2 output terminals, the first one is digital frequency output, the second one is digital phase difference output.

[0043] The phase detector can be divided into two parts, figure 1 The upper half is the frequency measurement circuit, and the lower half is the phase measurement circuit. The connection and work of the frequency measurement circuit are described as follows: the pin of the external input GPS_PPS signal is connected to the input terminal 1 of the frequency division circuit by 2, and the frequency division circuit plays two functions, the first function is to convert the external PPS signal into duty The ratio is 50% of...

example 1

[0052] f in example one clk =200MHz. The high-level and low-level width of the second pulse after frequency division by the 4-level 2-frequency division circuit is 8 seconds, so the capacity of the counter must be greater than 1.6×10 9 , the number of bits of high level counter 1 and low level counter 1 in example 1 is set to 32 bits. Therefore, the bit width of the frequency counting latch 1 is also 32 bits. The final frequency measurement value is output from the frequency count value latch 1, and the value in the latch is refreshed every 8 seconds, and the refresh time is the delay T after the rising edge and falling edge of the second pulse after 16 frequency division d2 long moments. When using, pay attention to reading the frequency count value latch 1 synchronously with the GPS PPS signal, and avoid the data refresh time.

[0053] The second part of the phase detector, namely figure 1 The phase error measurement circuit in the middle and lower parts realizes the p...

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Abstract

The invention discloses a digital phase detector for GPS taming crystal oscillator, comprising: a 2N frequency divider for obtaining a square wave pulse signal with a cycle of 2N seconds by dividing the frequency of the 1Hz PPS signal output by the GPS module; High and low level pulse width counters for wide counting; the input is connected to the externally provided frequency lock enable signal, connected to GPS and frequency-divided OCXO clock to output the second pulse clock of the internal second pulse signal; input the internal second pulse signal and GPS module output PPS signal, count the time difference between the rising edges, and output the phase difference counter clock of the phase difference count value; it is used to realize the OCXO crystal oscillator tracking the frequency of the GPS PPS signal, and simultaneously output the frequency value and the frequency count value latch of the phase error value register and a phase error value latch. The invention is convenient for timing design, and avoids the fuzzy problem of leading and lagging initial phase errors. The frequency and phase measuring counter adopts a serial counter scheme, so that the counting clock frequency is not affected by the number of counting digits.

Description

technical field [0001] The invention belongs to the field of phase detectors, in particular to a digital phase detector used for GPS taming crystal oscillators. Background technique [0002] The digital phase detector is an essential part of the digital phase-locked loop. Its basic function is to measure the time difference between the input clock signal and the edge of the reference clock signal, reflect the phase difference, and output the leading phase value and the lagging phase according to the leading and lagging conditions. value. The commonly used digital phase detector is a double D flip-flop phase detector, and the output signal has an analog output mode in which the pulse width represents the phase difference; there is also a digital output mode in which a timing counter counts the time difference of the edge and outputs a digital quantity; the time difference of the timing edge is generally used High-speed clock counts to measure the time difference, and there i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/085H03L7/18
Inventor 陈锟宁百齐朱正平孙奉娄蓝加平胡连欢林邓国
Owner SOUTH CENTRAL UNIVERSITY FOR NATIONALITIES
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