Trellis coded modulation method applicable to electrical interconnection system among high speed backplane chips

A grid code modulation, high-speed backplane technology, applied in transmission systems, digital transmission systems, electrical components, etc., can solve the problems of reduced information and data transmission efficiency, difficult to improve channel utilization system performance, etc., to improve anti-interference ability Effect

Active Publication Date: 2015-04-29
ZHEJIANG UNIV
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Problems solved by technology

Error correction coding will reduce the transmission efficiency of information data, so general error correction coding techniques such as Hamming codes, convolutional codes, and Reed-Solomon (Reed-Solomon, RS) codes improve information transmission performance ...

Method used

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  • Trellis coded modulation method applicable to electrical interconnection system among high speed backplane chips
  • Trellis coded modulation method applicable to electrical interconnection system among high speed backplane chips
  • Trellis coded modulation method applicable to electrical interconnection system among high speed backplane chips

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Embodiment 1

[0033] Embodiment 1, figure 1 A trellis coding modulation method applied to the electrical interconnection system between chips on a high-speed backplane is given; the method uses a sending end 1 and a receiving end 2; the sending end 1 includes a data parallel-to-serial module 11 and a trellis coding modulation module 12 and a forward feedback equalizer 13; the receiving end 2 includes a continuous time linear equalizer 21, a decision feedback equalizer 22, a soft-decision Viterbi decoding module 24, and a data serial-to-parallel module 25.

[0034] The data parallel-to-serial module 11 is used to convert the input N-bit parallel data a[1:N] into serial binary bits {X n ,X n =0,1}; trellis code modulation module 12 includes convolution encoder 121 and four-level pulse amplitude modulation circuit; as figure 2 Shown, the binary bit {X n ,X n =0,1} is sent to the convolutional encoder 121 as input, and each bit input passes through After the convolutional encoding of the...

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Abstract

The invention discloses a trellis coded modulation method applicable to an electrical interconnection system among high speed backplane chips, and relates to a trellis coded modulation technology applicable to the electrical interconnection system among the high speed backplane chips. According to the method, by the collaborative design of channel coding and signal modulation, coding gain can be obtained on the premises of not increasing the channel bandwidth and not lowering the transmission rate of effective information, so that the performance of serial single link among chips is improved. A sending end of a system comprises a data parallel/serial conversion, a trellis coded modulation and a forward feedback equalizer. The trellis coded modulation utilizes a measure combining the convolutional encoding and the four-level pulse amplitude modulation. A receiving end of the system comprises a continuous time linear equalizer, a decision feedback equalizer, a clock data recovery, a soft output Viterbi decoding and a data parallel/serial conversion. The update of a coefficient of a filter of the decision feedback equalizer is based on an error correction signal after the soft decision Viterbi decoding.

Description

technical field [0001] The present invention relates to the field of electrical interconnection system between high-speed backplane chips, specifically, Trellis Coded Modulation (TCM) technology is used in the electrical interconnection system between high-speed backplane chips, and the coding gain is obtained through the error correction ability of coding. Therefore, the reliability of the serial single-link system electrically interconnected between chips is improved. Background technique [0002] The performance of high-performance parallel computer systems is developing rapidly, and the demand for interconnection I / O bandwidth capabilities is increasing day by day. High-speed serializer / deserializer technology is replacing traditional parallel buses and becoming the mainstream of high-speed electrical interconnection interface technology between chips. High-speed serializer / deserializer technology uses internal integrated circuits to convert parallel data streams into se...

Claims

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Application Information

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IPC IPC(8): H04L1/00
CPCH04L1/006H04L1/065
Inventor 刘鹏史航王维东郭俊李顺斌邬可俊方兴吴东江国范谢向辉
Owner ZHEJIANG UNIV
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