Power Transistor Array Structure Integrated with Electrostatic Protection Circuit

Abstract

The invention discloses a power transistor array structure integrated with an electrostatic protection circuit. By replacing a part of the drain region of the unit structure 1 of the power transistor with the P+ region, the electrostatic protection circuit formed by SCR can be embedded. The gate is not connected to the gate of the unit structure 1, and the gate of the SCR is connected to the source of the unit structure 1; the present invention can improve the performance of the power transistor array without affecting the performance of the power transistor array and without changing the process. The electrostatic protection ability can effectively reduce the false triggering phenomenon of the thyristor, thereby expanding the safe working range of the power transistor array. At the same time, by setting the gate structure of the SCR to be recessed toward the drain region and injecting the P+ region into the body region on the source region side, the present invention can further reduce false triggering of thyristors and expand the safe operation of power transistor arrays. scope.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit, in particular to a power transistor array structure integrated with an electrostatic protection circuit. Background technique [0002] Power transistors are often used in high-voltage integrated circuits as output drive tubes that drive relatively large currents. Existing power drive tubes generally appear in the form of arrays. Such as Figure 1A Shown is a schematic diagram of the existing power transistor array layout structure; Figure 1B is along Figure 1A Schematic diagram of the cross-sectional structure of the unit structure at position A'A of ; a deep N well (DNW) 2 is formed on the silicon substrate 1, and the entire power transistor array is formed in the deep N well 2, and the unit of the power transistor Structure one is the NLDMOS device structure, including: [0003] A P-type body region 3 formed in the deep N well 2 . [0004] An N well 4 is formed in the deep N well 2 and...

AI Technical Summary

Problems solved by technology

Although embedding SCR can effectively improve the electrostatic protection capability of the output power transistor array, it will be a technical difficulty in this design to avoid false triggering of the SCR when the power transistor array is working normally. The higher the voltage and the higher the current, the easier it is for the SCR to trigger , so the embedded SCR will reduce the safe operating range (SOA) of the power transistor array

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