Method for manufacturing zinc-doped ultra shallow junction on surface of semiconductor substrate

Abstract

A method for preparing a zinc-doped ultra-shallow junction on a semiconductor substrate surface, which belongs to the technical field of semiconductor integration. In the method, a zinc-doped ultra-shallow junction is prepared on a semiconductor substrate surface in a diffusion manner from zinc in zinc oxide obtained by depositing an atomic layer. The method comprises: cleaning a semiconductor substrate surface (1); in an atomic layer deposition system, depositing a zinc oxide layer on a semiconductor substrate using an atomic layer deposition method (2); depositing a cap layer on the zinc oxide layer (3); diffusing zinc atoms in the zinc oxide layer to the semiconductor substrate surface by high-temperature annealing (4); and removing the cap layer and the zinc oxide layer (5). The method can be used for preparing ultra-shallow junctions of planar and non-planar semiconductor devices, and has the advantages of controllable junction depth and low damage to lattices of semiconductor substrates when used for doping of small-sized semiconductor devices.

Description

technical field [0001] The invention relates to a method for preparing an ultra-shallow junction of a semiconductor substrate, in particular to a method for preparing a zinc-doped ultra-shallow junction on the surface of a semiconductor substrate, and belongs to the technical field of semiconductor integration. Background technique [0002] As the core and foundation of the information industry, semiconductor technology is an important symbol to measure a country's scientific and technological progress and comprehensive national strength. In the past 40 years, CMOS integration technology has followed Moore's law to increase the working speed of devices, increase integration and reduce costs by reducing the feature size of devices. However, when the gate length of MOS devices is reduced to less than 90 nanometers, especially when entering the node of 65 nanometers and below, the source / drain region and the source / drain extension region are required to be correspondingly shall...

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Problems solved by technology

However, when the gate length of MOS devices is reduced to less than 90 nanometers, especially when entering the node of 65 nanometers and below, the source / drain region and the source / drain extension region are required to be correspondingly shallower, and the ultra-shallow junction can better improve the performance of the device. Short channel effect, but with the further improvement of device size and performance, junction leakage is a problem that needs to be solved more and more in ultra-shallow junction technology

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