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Method of forming contact plugs

A contact plug and contact hole technology, applied in the field of contact plug formation, can solve the problems of poor performance of contact plugs, affecting the performance of semiconductor devices, etc., and achieve the effect of avoiding electric leakage

Active Publication Date: 2017-12-01
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the present invention is that in the prior art, the performance of the formed contact plug at the common drain position is not good, thus affecting the performance of the subsequently formed semiconductor device

Method used

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  • Method of forming contact plugs
  • Method of forming contact plugs
  • Method of forming contact plugs

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Experimental program
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Embodiment Construction

[0037] In the prior art, the reasons for the poor performance of the formed source contact plug are as follows:

[0038] refer to figure 2 , with respect to the through hole between the interconnection metal layer and the interconnection metal layer, the height of the common drain contact hole 15 is at least equal to the sum of the height of the gate 11 and the height of the gate contact hole, so that the common drain The height of the contact hole 15 is much larger than the height of the through hole connecting two adjacent interconnection metal layers. Therefore, compared with the through hole between the interconnection metal layers, other source contact holes and drain contact holes In other words, the aspect ratio of the common drain contact hole 15 is large. refer to image 3 Therefore, there is an air gap 17 inside the common drain contact plug 16 formed by filling the common drain contact hole 15 with such a large aspect ratio with a tungsten metal layer. The exist...

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PUM

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Abstract

A forming method of a contact plug comprises the following steps: providing a semiconductor substrate, wherein a grid electrode is formed on the semiconductor substrate, a source electrode and a drain electrode are formed inside the substrate on bilateral sides of the grid electrode; forming a dielectric layer covering the semiconductor substrate, wherein the dielectric layer is divided into an upper portion and a lower portion, the thickness of the lower portion is equal to the height of the grid electrode, or the thickness of the lower portion is greater than the height of the grid electrode by a predetermined size, the density of the upper portion increases gradually from the top layer to the bottom layer of the upper portion, whereas the density all over the lower portion is identical and is greater than or equal to the density of the bottom layer of the upper portion; etching the dielectric layer to form a contact hole, wherein the top opening size of the contact hole is the biggest; filling a conductive layer inside the contact hole to form the contact plug, wherein the contact plug is electrically connected with the source electrode and the drain electrode. The forming method of the contact plug is able to increase the performance of the contact plug.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a method for forming a contact plug. Background technique [0002] As the production of integrated circuits develops towards ultra-large-scale integrated circuits, the circuit density inside integrated circuits is increasing, and the number of components contained is also increasing. This development makes the surface of the wafer unable to provide enough area to manufacture all the components. required interconnection wires. [0003] In order to meet the requirements of the interconnection line after the shrinkage of the components, the design of the interconnection metal layer has become a method usually adopted in the VLSI technology. Currently, conduction between the interconnection metal layer and devices in the substrate is achieved through contact plugs. [0004] In the prior art, two adjacent gates on the semiconductor substrate have a common drain. In the case of two adja...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L21/28
CPCH01L21/28H01L21/76816H01L2221/101
Inventor 何其暘黄敬勇张海洋
Owner SEMICON MFG INT (SHANGHAI) CORP