Bandgap voltage reference source circuit

Abstract

The invention relates to a bandgap voltage reference source circuit which comprises a reference circuit and a starting circuit, wherein the reference circuit comprises a fifth PMOS transistor, a six PMOS transistor, first NPN transistors, a second NPN transistor, a first resistor, a second resistor, and a third resistor, and is used for generating a voltage reference output Vref, the starting circuit provides starting offset voltage for a reference core circuit under degeneracy state and comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a first NMOS transistor and a second NMOS transistor. The circuit is simply structured, and practical and is accurate in output.

Description

technical field [0001] The invention relates to a CMOS bandgap reference voltage source circuit, in particular to a CMOS bandgap reference voltage source circuit without an operational amplifier, and belongs to the technical field of analog integrated circuits. Background technique [0002] The basic principle of a bandgap voltage reference is to use two voltages with opposite temperature coefficients to add with appropriate weights to produce a voltage with zero temperature coefficient. A bipolar junction transistor (BJT) has the following two properties: the base-emitter voltage VBE of a bipolar transistor is inversely proportional to the absolute temperature; at different collector currents, the base-emitter voltage of two bipolar transistors Pole voltage difference ΔVBE is proportional to the absolute temperature. Therefore bipolar transistors are usually at the heart of forming a bandgap reference voltage. [0003] In the field of analog integrated circuit or mixed-si...

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Problems solved by technology

[0007] The bandgap reference voltage circuit with the above structure has the problem of large area because it includes the error amplifier and the corresponding bias circuit, and the offset voltage and noise of the error amplifier itself will also be added to the reference voltage output terminal (Vref)

Since the reference voltage is generated by a branch alone, figure 1 The mirror mismatch between the PM3, PM1 and PM2 mirror current sources will also increase the offset voltage of the reference voltage and increase the layout area

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