Method for forming semiconductor device

Abstract

The invention provides a method for forming a semiconductor device. The method comprises a method of forming metal material layers in the grooves in semiconductor substrates and on the semiconductor substrates, using the tool cutting process to remove a part of metal material layers such that the surfaces of the metal material layers in the grooves are level with the surfaces of the semiconductor substrates, and then allowing two semiconductor substrates to be bonded and connected. After the tool cutting process is used to remove a part of metal material layers, the crystalline grains at the surface of the residual metal material layer are arranged in a disorderly way, a large number of faults appearance in the crystalline grains, the shape of the cells of the crystalline grains is abnormal, a large number of atomic vacancies appear in the cells, in the subsequent bonding process of the above structure, the atomic diffusion efficiency between the metal material layers on the two semiconductor substrates can be raised, thus while the bonding strength between the metal material layers is ensured, the temperature of the bonding process can be effectively reduced, and thus the damage of the semiconductor substrates and the device damage in the semiconductor substrates caused by high temperature is avoided.

Description

technical field [0001] The invention relates to the field of semiconductor formation, in particular to a method for forming a semiconductor device. Background technique [0002] With the rapid development of the information industry, the feature size (CD) of integrated circuits has been continuously reduced, and the manufacturing process of integrated circuit chips has also been miniaturized. The development of integrated circuit chip preparation technology has prompted integrated circuit packaging technology to continuously pursue the demand for higher performance, more functions, smaller size, lower power consumption and cost. [0003] In the development of 3D (3-dimensional) integrated circuit packaging technology, bonding technology is a commonly used packaging technology. refer to Figure 1~4 As shown, the so-called bonding technique includes: after forming a groove 11 on the wafer 10 and filling the groove 11 with the metal material 12, the excess metal material on th...

AI Technical Summary

Problems solved by technology

During the bonding process, due to the high temperature and high pressure, the local wafers are prone to expansion and warping, which will not only affect the bonding effect (such as the alignment accuracy deviation of the metal material layers of the two wafers), but also It will damage the wafer and the performance of the devices in the wafer, resulting in performance defects of the final semiconductor device

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