Touch panel array
A touch panel and array technology, applied in the field of microelectronics, can solve the problems of having to open a hole on the front to make a physical HOME button, limiting the effective display area of a mobile phone, and unable to achieve substantial improvement, so as to achieve miniaturization and improve fingerprints. Recognition accuracy, easy-to-achieve effects
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Embodiment 1
[0045] A touch panel array, including a fingerprint identification area supporting fingerprint identification mode and touch mode. The touch panel array is composed of several array elements arranged in a two-dimensional matrix, and the array elements in this embodiment are enclosed areas surrounded by any two adjacent scanning lines and any two adjacent sensing lines.
[0046] In this embodiment, each array element in the fingerprint identification area corresponds to the first scan line with the earlier timing and the second scan line with the later timing, as shown in figure 1 As shown, each array element includes:
[0047] Capacitive electrodes (in this embodiment, self-capacitance electrodes) are used to form inductive capacitance at the fingerprint contact;
[0048] A charging switch, one end is connected to the capacitor electrode, and the other end is connected to the first scanning line corresponding to the array element, and the charging switch is turned on when a h...
Embodiment 2
[0071] It is the same as Embodiment 1, except that the conversion module has a two-stage amplification function.
[0072] like Figure 5 As shown, the conversion module of this embodiment includes a third thin film transistor Q3 and a fourth thin film transistor Q4; The source of the thin film transistor Q4 is used as an input terminal and connected to the corresponding second scanning line L2 for voltage sampling, and the drain is used as an output terminal and connected to the corresponding sensing line L3 to output the induced current;
[0073] In this embodiment, each array element is correspondingly provided with a ground line L4, wherein the drain of the third thin film transistor Q3 is connected to the ground line L4, and the source is connected to the gate of the fourth thin film transistor Q4, and the source of the third thin film transistor Q3 is connected to the ground line L4. The terminal is connected to the source of the fourth thin film transistor Q4 through a ...
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