Clock phase control circuit

Abstract

A clock phase control circuit comprises a clock input stage, a capacitor, a level detection circuit, a pull-up circuit, a pull-down circuit, a clock output stage and a logic control circuit. The output end of the clock input stage and the input end of the level detection circuit are connected at an A point, and the A point is also connected with the output ends of the capacitor, the pull-up circuit and the pull-down circuit. The other end of the capacitor is connected with a fixed DC level, and the level detection circuit detects the voltage of the A point and outputs a detection signal to the clock output stage. The logic control circuit is connected with the clock input stage, the pull-up circuit and the pull-down circuit, and controls the pull-up circuit and the pull-down circuit to be turned on at the high level time and the low level time of a clock respectively. The clock phase control circuit of the present invention starts to charge and discharge the capacitor at the rising or falling edge of the clock, thereby causing the time delay of a signal output edge. The clock phase control circuit is simple in circuit principle, is convenient to integrate in an integrated circuit existing technology, does not need to the support of a peripheral separating electronic component, realizes a clock buffer function, and also enables the circuit cost to be reduced.

Description

technical field [0001] The invention belongs to the field of electronic circuits and relates to a clock phase control circuit. Background technique [0002] The clock frequency refers to the basic frequency of the clock in the synchronous circuit, which is measured by "several cycles per second", and the measurement unit is the SI unit hertz (Hz). Numerous transistors in digital circuits and analog circuit chips all work in the switch state, and their conduction and shutdown actions are all carried out in accordance with the rhythm of the clock signal. If the clock frequency is too high, the state of the transistor may not change in time, resulting in deadlock or random misoperation. At the same time, due to the needs of the working state of the circuit, the phase of the clock needs to be adjusted. The existing clock phase adjustment usually relies on a separate chip, which increases the cost and occupies the area of ​​the PCB board. Contents of the invention [0003] In...

AI Technical Summary

Problems solved by technology

If the clock frequency is too high, the state of the transistor may not change in time, resulting in deadlock or random misoperation

At the same time, due to the needs of the working state of the circuit, the phase of the clock needs to be adjusted. The existing clock phase adjustment usually relies on a separate chip, which increases the cost and occupies the area of ​​the PCB board.

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