NAND flash memory error control code structure and error code control method thereof

Abstract

The present invention discloses an NAND flash memory error control code structure, comprising an ECC coder having a bit rate of 0.4 to 0.9, an ECC decoder having a bit rate of 0.4 to 0.9, and an NAND flash memory controller. The present invention further discloses an error code control method of the NAND flash memory error control code structure, comprising the following steps: 1. acquiring to NAND flash memories under different processes, acquiring a relationship between a raw bit error ratio (RBRR) and erasable times of the flash memory; 2. calculating an acceptable RBER when UBER is less than 10 to 15; 3. calculating the erasable times of the flash memory under different RRERs according to the previously acquired relationship between the erasable times and the RBER of the flash memory under different processes; 4. calculating a non-error bit integral information capacity of the flash memory; and 5. selecting a bit rate of the ECC. According to the present invention, the non-error bit integral information capacity can be ensured to the maximum and the long-term stability of the NAND flash memory can be ensured.

Description

technical field [0001] The invention relates to an electronic communication technology, in particular to an error control code structure of a NAND flash memory and an error code control method thereof. Background technique [0002] In the past ten years, NAND flash memory has been widely used in data storage systems due to its advantages of high performance, low power consumption, large capacity and non-volatility. [0003] However, with the advancement of technology, the storage density of flash memory has increased significantly, and the bit error rate of flash memory has risen sharply. From more than 60 nanometers to more than 40 nanometers, the bit error rate has increased by more than three orders of magnitude; from more than 40 nanometers to more than 30 nanometers, the bit error rate has increased by 32 times; and the process has progressed to more than 20 nanometers , the bit error rate increased by 4.5 times. As the storage density of NAND flash memory further inc...

AI Technical Summary

Problems solved by technology

Faced with a higher and higher bit error rate, this scheme can improve the error correction performance of the error control code, but the hardware complexity also increases with the bit rate, and may eventually face technical obstacles

Moreover, the error control code with a high code rate builds a system with a high initial capacity and a short life, which cannot meet the requirements of long-term stable storage capacity applications.

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