3 results about "Raw bit error rate" patented technology

The application relates to the technical field of NAND flash error correction, in particular to a high-capacity NAND flash error correction method and system based on a layered ECC (Error Correction Code). The method comprises the following steps: obtaining physical storage structure information of the high-capacity NAND flash, wherein the physical storage structure information comprises a plurality of storage blocks, a plurality of storage pages and original error code rate characteristics of each storage layer. The application realizes accurate error correction for the differences of different storage layers by designing a two-level layered architecture of a strong error correction layer and an adaptive error correction layer and dynamically configuring an error correction strategy according to the original error code rate characteristics of each storage layer. The strong error correction layer uses Reed-Solomon error correction code to reliably store user data. The error correction code can show good error correction ability when facing random errors and burst errors based on Galois field arithmetic operation, the coding gain is increased by about 3 dB compared with a single-layer scheme, and the uncorrectable error frame rate of the user data is effectively reduced.

This application discloses a flash memory level testing method, apparatus, device, and medium. The method includes: acquiring real-time test values ​​corresponding to the flash memory core parameters and test environment parameters of the flash memory device; wherein the flash memory core parameters include erase / write cycles, and the test environment parameters include temperature parameters; performing a normalization operation based on the real-time test values ​​to obtain normalized weight coefficients; dividing a preset value range to obtain multiple weighted sub-ranges; determining a target raw bit error rate (BER) grading threshold list based on the normalized weight coefficients and the multiple weighted sub-ranges; acquiring the real-time raw BER; and determining the target flash memory level of the flash memory device based on the real-time raw BER and the target raw BER grading threshold list. This technical solution integrates the dynamic influence of flash memory core parameters and test environment parameters to construct a real-time dynamic grading method, achieving accurate determination of the flash memory level of the flash memory device.

The present application discloses a method and device for reliability testing of a memory cell, and a computer-readable storage medium. The method for reliability testing of the memory cell comprises: applying read voltages to a memory cell on the basis of a read voltage sequence; upon applying each of the read voltages, recording a raw bit error rate of data in the memory cell; determining, as a valid window boundary, the read voltage corresponding to the raw bit error rate equal to a preset threshold; determining a length of a valid window on the basis of the valid window boundary; and determining a test result of the memory cell on the basis of the length of the valid window, the test result being used for representing the reliability of the memory cell during data storage.