11 results about "Raw bit error rate" patented technology

The invention discloses a PON (Passive Optical Network) network fault detection method, device and equipment and a storage medium, the PON network fault detection method can be applied to Fiber To Room (FTTR), enterprise-level Fiber To Room-Bus (FTTR-B) and broadband fusion terminal products, and the PON network fault detection method comprises the following steps: obtaining an original bit error rate and link quality data carrying a sub-machine identifier, the sub-machine identifier is a unique identifier corresponding to the FTTR sub-machine; performing fault detection based on the original bit error rate and the link quality data, and determining a fault detection result corresponding to the sub-machine identifier; and when the fault detection result is that a fault exists, executing fault alarm processing based on the original bit error rate and a target bit error rate threshold. According to the method, the problems that the fault source cannot be determined in the PON network, the fault detection is inaccurate and the alarm is not timely can be solved.

The invention discloses a flash memory grade test method, device and equipment and a medium. The method comprises the following steps: acquiring real-time test values respectively corresponding to flash memory core parameters and test environment parameters of flash memory equipment; wherein the flash memory core parameters comprise erasing times, and the test environment parameters comprise temperature parameters; performing normalization operation based on the real-time test value to obtain a normalized weight coefficient; dividing a preset value interval to obtain a plurality of weight subintervals, and determining a target original bit error rate grading threshold list based on the normalized weight coefficient and the plurality of weight subintervals; and obtaining a real-time original bit error rate, and determining a target flash memory level of the flash memory device based on the real-time original bit error rate and the target original bit error rate grading threshold list. According to the technical scheme, the dynamic influences of the flash memory core parameters and the test environment parameters are integrated, a real-time dynamic grading mode is constructed, and accurate judgment of the flash memory grade of the flash memory equipment is achieved.

In some implementations, a storage device may perform a read operation using a first read voltage. The storage device may identify a read error associated with the read operation. The storage device may identify a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER). The storage device may perform a write operation using a program verify voltage that is based on the difference.

A processing device in a memory sub-system determines a current temperature of a memory device and accesses historical transition data for management units at a plurality of temperatures. The processing device determines a transition time based on the historical transition data and current temperature, sets a scan frequency based on the transition time, and traverses management units at the scan frequency to maintain the management units in a transient state with lower raw bit error rate. The scan frequency may be set to be less than the transition time to prevent management units from transitioning to a stable state with higher raw bit error rate.

This invention discloses a dynamic error correction method, controller, and storage system suitable for 3D NAND flash memory, belonging to the field of semiconductor storage technology. It includes: an encoding stage: polar code encoding of the data to be written to the 3D NAND flash memory to obtain a codeword sequence of length N; a decoding stage: calculating the LLR value of each bit of the data of length N read from the 3D NAND flash memory; after setting the list length of the SCL decoding algorithm, inputting the N-bit LLR values ​​into the SCL decoding algorithm to achieve decoding; setting the list length of the SCL decoding algorithm includes: obtaining the bit error rate of the SCL decoding algorithm at different list lengths under the current raw bit error rate of the 3D NAND flash memory, selecting list lengths with bit error rates lower than a preset performance threshold, and setting the list length of the SCL decoding algorithm to the selected minimum length. This invention is adapted to the error characteristics of 3D NAND flash memory and can reduce overhead while ensuring that error correction requirements are met.

In some implementations, a storage device may perform a read operation using a first read voltage. The storage device may identify a read error associated with the read operation. The storage device may identify a difference between the first read voltage and a second read voltage, the second read voltage associated with a reduced raw bit error rate (RBER). The storage device may perform a write operation using a program verify voltage that is based on the difference.

Facility, showing: a memory array (502) comprising a plurality of memory cells (701) with reversible resistivity; and a control circuit in communication with the memory array (502), wherein the control circuit (502) is configured to: to read a group of selected memory cells (701) using a referenced read; Decode data read from the group using referenced reading with a first error correction code (ECC) mode capable of correcting up to a first number of bits in the group; to read the group of selected memory cells (701) using a self-referencing read in response to an error, in order to decode the data in the group using the first ECC mode; and Decoding data read from the group using self-referencing with a second ECC mode capable of correcting up to a second number of bits in the group, where the second number of bits is greater than the first number of bits, characterized in that: the first ECC mode exhibits an initial error correction rate for a given raw bit error rate; and The second ECC mode has a second error correction rate that is greater than the first error correction rate for the given raw bit error rate, with data read using self-referenced read having a lower raw bit error rate than data read using referenced read, and a reduction in the raw bit error rate reducing the error correction rate in the second ECC mode.

This disclosure describes techniques for estimating raw bit error rates of data stored in a set of memory cells. Encoded data is read from a set of memory cells. A first population value is obtained based on a first number of memory cells in the set of memory cells having a read voltage within a first range of read voltages, each read voltage representing one or more bits of the encoded data. It is determined that an estimated raw bit error rate of the data satisfies a first threshold. The determination is made using a first trained machine learning model and based in part on the first population value. In response to the determination that the estimated raw bit error rate satisfies the first threshold, a first media management operation is initiated.

This application discloses a flash memory level testing method, apparatus, device, and medium. The method includes: acquiring real-time test values ​​corresponding to the flash memory core parameters and test environment parameters of the flash memory device; wherein the flash memory core parameters include erase / write cycles, and the test environment parameters include temperature parameters; performing a normalization operation based on the real-time test values ​​to obtain normalized weight coefficients; dividing a preset value range to obtain multiple weighted sub-ranges; determining a target raw bit error rate (BER) grading threshold list based on the normalized weight coefficients and the multiple weighted sub-ranges; acquiring the real-time raw BER; and determining the target flash memory level of the flash memory device based on the real-time raw BER and the target raw BER grading threshold list. This technical solution integrates the dynamic influence of flash memory core parameters and test environment parameters to construct a real-time dynamic grading method, achieving accurate determination of the flash memory level of the flash memory device.

The present application discloses a method and device for reliability testing of a memory cell, and a computer-readable storage medium. The method for reliability testing of the memory cell comprises: applying read voltages to a memory cell on the basis of a read voltage sequence; upon applying each of the read voltages, recording a raw bit error rate of data in the memory cell; determining, as a valid window boundary, the read voltage corresponding to the raw bit error rate equal to a preset threshold; determining a length of a valid window on the basis of the valid window boundary; and determining a test result of the memory cell on the basis of the length of the valid window, the test result being used for representing the reliability of the memory cell during data storage.