37 results about "Raw bit error rate" patented technology

An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled. In an embodiment of the present invention, the first and second counters are logarithmic counters that include overflow protection. The counter values are output to a processing device to perform the BER calculation in an embodiment of the present invention. A plurality of BER values is then obtained for corresponding offsets. A subset of the plurality of BER values corresponding to the plurality of offsets is selected. An inverse of the standard normal cumulative distribution (NormSlnv) function for respective BER values is calculated. Two linear fits on the transformed BER values and offsets are performed to obtain the x-intercepts that correspond to a DJ component and the slopes corresponding to a RJ component. The DJ and RJ components are used with the Fibre Channel jitter model equation to predict BER as a function of transition density and offset value.

Systems and methods for correcting errors in data read from memory cells include a memory controller, which includes an encoder, and a decoder. The memory controller is configured to adjust a correctable raw bit error rate limit to correct different bit error rates occurring in data read from the memory cells. The correctable raw bit error rate limit is adjusted by switching the decoding between hard-decision decoding and soft-decision decoding, wherein a number of soft bits allocated for message values can be changed during soft-decision decoding. The correctable raw bit error rate is adjusted by changing the code-rate within the memory system while making virtual adjustments to the same encoder and decoder.

A method and system for determining a receiver power for a required bit error rate (BER) in an optical communication systems is disclosed. A signal is transmitted using an initial transmitter power and is received at a receiver. A BER contour diagram is created by measuring high BER values and approximating low BER values from the high BER values. The optimum decision threshold and/or sampling phase is determined from the contour diagram and the BER is calculated at the optimum decision threshold and/or at the optimum sampling phase. If the calculated BER is not close to or equal to the required BER, the transmitter power is adjusted until the calculated BER is close to or equal to the required BER. The receiver power is then calculated from the transmitter power or directly measured from the received signal.

A dynamic power adjusting device for a Viterbi decoder is disclosed. The device includes a processing unit for receiving a plurality of data to be decoded, detecting whether the data to be decoded have any bit errors, and estimating a number of the bit errors of the data. The device further includes a control unit for receiving the bit errors and the number of the bit errors of the data detected by the processing unit, so as to enable the Viterbi decoder to perform decoding, and disable the Viterbi decoder after the Viterbi decoder has performed the decoding the number of times equivalent to the number of the bit errors. By way of the dynamic adjustment technique, coupled with the bit-error detection and estimation, workload of the Viterbi decoder in operation is capable of being adjusted according to bit error rate (BER) such that less power is consumed in a decoding process.

A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

A storage system includes: a control processor unit, configured to: initiating a read of a raw data page, having correctable errors, calculating a raw bit error rate (RBER) (EQ1) by correcting the correctable errors to become corrected data and comparing raw data with the corrected data, and calculating a correction model characterization based on the RBER (EQ1); and a non-volatile storage array,coupled to the control processor unit, configured to store a processed data page in a physical block with the raw data page; and wherein the control processor unit is further configured to apply the correction model characterization to the raw data page in the physical block.

A solid state drive with a capability to select physical flash memory blocks and erasure and programming methods according to requirements of an application using storage in the solid state drive. A wear-out tracker in the solid state drive counts programming and erase cycles, and a raw bit error rate tracker in the solid state drive monitors raw bit errors in data read from the solid state drive. The application provides, to the solid state drive, requirements on an allowable retention time, corresponding to the anticipated storage time of data stored by the application, and on an average response time corresponding to programming and read times for the flash memory. The solid state drive identifies physical flash memory blocks suitable for meeting the requirements, and allocates storage space to the application from among the identified physical flash memory blocks.

The present invention discloses an NAND flash memory error control code structure, comprising an ECC coder having a bit rate of 0.4 to 0.9, an ECC decoder having a bit rate of 0.4 to 0.9, and an NAND flash memory controller. The present invention further discloses an error code control method of the NAND flash memory error control code structure, comprising the following steps: 1. acquiring to NAND flash memories under different processes, acquiring a relationship between a raw bit error ratio (RBRR) and erasable times of the flash memory; 2. calculating an acceptable RBER when UBER is less than 10 to 15; 3. calculating the erasable times of the flash memory under different RRERs according to the previously acquired relationship between the erasable times and the RBER of the flash memory under different processes; 4. calculating a non-error bit integral information capacity of the flash memory; and 5. selecting a bit rate of the ECC. According to the present invention, the non-error bit integral information capacity can be ensured to the maximum and the long-term stability of the NAND flash memory can be ensured.

The invention discloses a data recovery method, device and system for a flash memory, storage data and verification information are stored in the flash memory, before data are written into the flash memory, the storage data can be decomposed to obtain decomposed data, and the verification information can be obtained according to the decomposed data. When the data is read, the flash memory can be read based on the first read voltage to obtain first original data, the first original data is subjected to ECC decoding and error correction to obtain first error correction data, and the first original data and the first error correction data are utilized to compensate the third read voltage to obtain a third theoretical optimal read voltage. The read voltage required by the read operation of the flash memory can be determined without additional read operation required by a traditional re-read error correction method, and the original error rate is effectively reduced.