38 results about "Raw bit error rate" patented technology

There is provided a receiver comprising a processing unit, a communications unit for receiving frames including training sequence symbols or pilot symbols, the processing unit being configured to use Cyclic Redundancy Check for detecting errors in the received frames. When no errors in a given frame are discovered on the basis of the Cyclic Redundancy Check, the processing unit is further configured to define a TSC, training sequence code, bit error rate for the bursts of the given frame on the basis of the training sequence symbols or the pilot symbols; to define an upper limit for the TSC bit error rate; and to determine the given frame to be bad when the TSC bit error rate for the bursts of the given frame is greater than the upper limit of the TSC bit error rate.

An apparatus and method provides prediction of BER for an interface between ICs, such as a processor and a memory device, without using special test equipment. A known data pattern or PRBS is transmitted to a receiver, which compares the received data values with expected data values to determine if a bit error has occurred in an embodiment of the present invention. A center of data eye and the edge of the data eye are sampled (over sampled) in order to determine if a bit error has occurred in an alternate embodiment of the present invention. A first counter is used to count the total number of bits sampled and the second counter is used to count the number of errors that occurred in the total number of bits sampled.

System and method of estimating radio channel bit error rate (BER) in a digital radio telecommunications system wherein the soft output of the turbo decoder is used as pointer or index to look-up-tables containing the bit-wise BER of a certain bit in the data field of the received frame. A quantizer quantizes the received data frame and the quantized bit operates on a switch which selects the appropriate look-up-table. By means of accumulation and scaling the average BER of a certain amount of bits are calculated. Decoding bit-errors may occur but as they are submitted to posterior probability estimation, systematic errors which normally happen at low SNR are avoided.

A computer-implemented method for writing data to a first media using a set of data structures to reduce potential errors when reading the data from the first media is described. The method includes writing, user data to a set of memory cells in the first media; and storing, in response to writing the user data to the set of memory cells, a first set of parity bits associated with the user data in a first buffer that is held within a second media separate from the first media and is a different type than the first media, wherein the first set of parity bits provide error correction information for correcting errors introduced to the user data while stored in the set of memory cells or read from the set of memory cells.

The invention discloses an RAID stripe reconstruction method applied to a solid state disk. The method is used for recombining physical block groups of an RAID memory array to form a new RAID stripe.The method comprises the steps of S1, detecting original error rates of physical blocks and updating and recording the original error rates in a block state table; S2, according to the original errorrates in the block state table, obtaining weak block information; S3, obtaining a weak block quantity through the block state table, and performing stripe organization for the physical blocks; and S4,performing block internal stripe organization in a staggered way for LSB pages and MSB pages of the physical blocks in a same RAID stripe. According to the RAID stripe reconstruction method, dynamicadjustment of the RAID stripe of the solid state disk is realized; data loss is avoided; storage space waste is avoided; the reliability of the solid state disk is improved; and the service life of the solid state disk is prolonged. Meanwhile, the invention furthermore discloses the solid state disk. The solid state disk comprises the RAID memory array and a controller used for performing adaptiveadjustment on the RAID memory array and managing data stored in the array.

The invention relates to an interleaving and error-correcting method for reducing bit error rate of a volume hologram storage system, comprising the following steps of: (1) firstly, carrying out error correction coding on data to be stored from three dimensionalities including a row direction, a line direction and among data pages; (2) after error correction coding, carrying out matching interleaving within data pages, and then carrying out block interleaving among the data pages to rearrange the sequence among the data pages; and (3) restoring the data obtained in the volume hologram storagesystem into original data by sequentially carrying out detection and postprocessing, demodulation and de-interleaving, and clearing error correction codes. In the invention, because the methods of matching interleaving among within pages and block interleaving among data pages are adopted and the Reed Solomon error correcting code is used for error correction from three dimensionalities, the influence of nonuniform distribution of bit error rate within pages and among data pages is eliminated, burst errors are overcome, random errors are corrected, and iteration decoding can be carried out inthree directions so that the bit error rate after correction is greatly reduced. The invention can be widely applied in various error modes of volume hologram storage channels.