A kind of preparation method of silicon nanowire

Abstract

The invention provides a silicon nanowire preparation method comprising steps of: providing a silicon substrate and etching the silicon substrate to form multiple trenches, wherein the silicon substrate between the trenches is defined as fin structures; depositing a first silicon dioxide layer and a silicon nitride layer, removing the silicon nitride layer on the tops of the fin structures by using chemical mechanical polishing technology, and etching a part of the silicon nitride layer in the trench in order to make the surface of the silicon nitride layer an arc shape; depositing a second silicon dioxide layer and etching the second silicon dioxide layer in order to make the surface of the second silicon dioxide layer an arc shape; epitaxial growing the silicon; etching the fin structures until the fin structures is as high as the first silicon dioxide layer, and etching the silicon in order to form a cylindrical silicon nanowire; and removing the silicon nitride layer in order to suspend the silicon nanowire. The silicon nanowire prepared by the silicon nanowire preparation method can be in a cylindrical shape. The silicon nanowire preparation method is compatible with MOS technology, simple, convenient, and short in cycle, and has good application prospect in the field of semiconductor devices.

Description

technical field [0001] The invention relates to the technical field of semiconductor technology, in particular to a method for preparing silicon nanowires. Background technique [0002] For more than half a century, the rapid development of the integrated circuit industry has provided hardware guarantee for the information age. MOS devices are important components in the field of integrated circuits. In 1925, J. Lilienfirld proposed the principle behind the field effect transistor. In 1948, the first field effect transistor was born in the laboratory. Scaling down of devices has been going on throughout the history of integrated circuits because of the benefits of higher on-state current, higher speed, and smaller area that smaller-sized devices can bring. [0003] However, when the feature size of traditional MOS devices is reduced to the nanometer scale, various negative effects begin to emerge. Among them, since the equivalent gate oxide thickness cannot be reduced in ...

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Problems solved by technology

[0007] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for preparing silicon nanowires, which is used to solve the problem that the silicon nanowires prepared in the prior art are triangular, which makes the turn-on voltage of the device difficult to control, and the triangular The sharp corners cause a large leakage current from the channel to the gate

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