Interconnection material for stacking of three-dimensional packaging chips

Abstract

The invention discloses an interconnection material for the stacking of three-dimensional packaging chips, and belongs to the field of chip interconnection materials. The material contains the following components: 3-5% of submicron Fe particles, and 5-8% of carbon nano tubes, wherein the remaining component is Sn. Sn powder sold on market, mixed rosin resin, a thixotropic agent, a stabilizer, an active adjuvant and an active agent are employed and mixed completely, and then the submicron Fe particle is added, and finally the carbon nano tubes are added. The mixture is completely stirred for preparing a paste interconnection material containing the Fe particles and carbon nano tubes. The technology of precise silk-screen printing and the technology of reflow soldering are employed for preparing convex points on the surfaces of chips, and the vertical stacking interconnection of chips under the condition of certain pressure (1MPa-10MPa) and temperature (235 DEG C -260 DEG C), thereby forming reinforced concrete structure solder points. The material is high in reliability, and can be used for the stacking of the three-dimensional packaging chips.

Description

technical field [0001] The invention relates to an interconnection material used for three-dimensional packaging chip stacking, and belongs to the field of chip interconnection materials. This interconnect material is mainly used in the field of high reliability requirements for three-dimensional packaging, and is a new type of interconnect material with high performance. Background technique [0002] Since Moore's Law was proposed, it has been considered to guide the development direction of electronic device technology, but with the increasing integration of a single chip, it seems that Moore's Law is difficult to continue to use. The emergence of three-dimensional packaging chip stacking technology can greatly delay the expiration time of Moore's Law. Three-dimensional packaging, that is, stacking chips layer by layer in three-dimensional space, can achieve the dual functions of reducing chip size and improving data transmission speed. [0003] Chips are stacked vertica...

AI Technical Summary

Problems solved by technology

[0005] However, intermetallic compounds have their own disadvantages: (1) Since intermetallic compounds will shrink in volume during the interdiffusion of solid-liquid elements, there will be obvious voids in the interface area, and the voids will become the source of crack initiation in solder joints; (2) Due to the mismatch of the linear expansion coefficient of the material during the service period of the three-dimensional packaging structure, the intermetallic compound solder joints tend to become stress concentration areas. When the stress concentration reaches a certain level, the solder joints will fail due to fatigue

The reliability of the three-dimensional packaging structure can be significantly improved by studying new interconnect materials, but there is currently a lack of relevant reports in the international community on research in this area

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