Method for forming semiconductor structure

A technology of semiconductor and dummy gate structure, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as poor reliability and unstable performance of fin field effect transistors

Active Publication Date: 2016-01-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, the performance of fin field effect transistors formed by the prior art is not stable and the reliability is poor

Method used

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  • Method for forming semiconductor structure
  • Method for forming semiconductor structure
  • Method for forming semiconductor structure

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Experimental program
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Embodiment Construction

[0031] As mentioned in the background, the FinFETs formed in the prior art have unstable performance and poor reliability.

[0032] In order to further reduce the size of the semiconductor device and increase the integration of the semiconductor device, a high-K metal gate (High-K Metal Gate, HKMG for short) structure is introduced into the transistor. Please continue to refer figure 1 , the gate structure 103 includes: a gate dielectric layer located on the sidewall and top surface of the fin 101 , and a gate layer located on the surface of the gate dielectric layer. When the gate structure 103 is a high-K metal gate structure, the material of the gate dielectric layer is a high-K dielectric material, and the material of the gate layer is metal.

[0033]The high-K metal gate structure needs to be formed by a gate last (GateLast) process, that is, a dummy gate structure straddling the fin 101 is first formed on the sidewall and top surface of the fin 101, and then the dummy g...

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PUM

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Abstract

Provided is a method for forming a semiconductor structure. The method comprises steps of: providing a substrate provided with a core region and a peripheral region; forming a first fin portion and a second fin portion on the surface of the substrate, where in the first fin portion is located in the core region and the second fin portion is located in the peripheral region; forming an isolating layer on the surface of the substrate, wherein the surface of the isolating layer is lower than the top surface of the first fin portion and the top surface of the second fin portion, and the isolating layer covers a part of sidewall surface of the first pin portion and a part of sidewall surface of the second pin portion; forming first oxide layers on the sidewall surface and the top surface of the first pin portion and the sidewall surface and the top surface of the second pin portion after the isolating layer is formed; oxidizing the first oxide layer in the core region in order that the oxygen ion content of the surface, in contact with the first fin portion, of the first oxide layer is increased; and etching the first oxide layer of the core region after the oxidation. The semiconductor structure formed by the method is good in performance and morphology and stable in performance.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure. Background technique [0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are developing towards higher element density and higher integration. As the most basic semiconductor device, transistors are currently being widely used. Therefore, with the increase of component density and integration of semiconductor devices, the gate size of planar transistors is getting shorter and shorter. The ability of traditional planar transistors to control channel current Weakened, resulting in short channel effect, resulting in leakage current, and ultimately affecting the electrical performance of semiconductor devices. [0003] In order to overcome the short-channel effect of the transistor and suppress the leakage current, a Fin Field Effect Transistor (FinFET) is proposed in...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/336
Inventor 赵杰
Owner SEMICON MFG INT (SHANGHAI) CORP
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